VCD output from generated verilog

[timksf]

I just wanted to ask if there is a built-in way to get VCD from the generated verilog? This would be very useful for getting VCD for designs with TriState modules.

[timksf]

Well, I just had another look at the user guide and found the +bscvcd argument.

[quark17]

Yes. You can also control the hierarchy levels that are dumped, specify the filename, and choose FSDB format as well as VCD.

When you link with bsc -e, it uses a top-level file called main.v which can be found in the repo here. In lines 63-95, there is code to check the plusargs and use macro definitions, to control change dumping.

The macros BSV_DUMP_LEVEL and BSV_DUMP_TOP can be provided at link time (the bsc -e command), to control the levels of hierarchy:

$dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);

You can specify the filename with an equalsign after bscvcd in the plusarg:

if ($value$plusargs("bscvcd=%s", filename))

And you can dump FSDB format with bscfsdb:

if ($value$plusargs("bscfsdb=%s", filename))

And you can manually edit the main.v file to add any other features that aren't there. At the moment bsc -e doesn't let you specify compiling without the built-in main.v, but I would like to add an option (like -no-include-main) that would let you provide your own top-level. You can half-automate that, by manually calling the appropriate bsc_build_vsim_* script, that BSC uses under the covers.