Merge pull request #77 from jaysongiroux/amd_VMCB_PR

Amd vmcb

data/amd/register/vmcb/000h.yml

@@ -2,7 +2,7 @@
   long_name: "000h (vector 0)"
   purpose: |
       "
-      Intercept reads of CR0–15, respectively
+      000h
       "
   size: 32
   arch: amd64
@@ -17,21 +17,21 @@
         component: vmcb
 
   fieldsets:
-    name: latest
-    condition: "Fieldset valid on latest version of the AMD architecture"
-    size: 32
+    - name: latest
+      condition: "Fieldset valid on latest version of the AMD architecture"
+      size: 32
 
-    fields:
-      - name: "Bits 15_0"
-        long_name: "Intercept reads of CR0–15, respectively" 
-        lsb: 0
-        msb: 15
-        readable: True
-        writable: True
+      fields:
+          - name: "Bits 15_0"
+            long_name: "Intercept reads of CR0–15, respectively" 
+            lsb: 0
+            msb: 15
+            readable: True
+            writable: True
 
-      - name: "Bits 31_16"
-        long_name: "Intercept writes of CR0–15, respectively" 
-        lsb: 16
-        msb: 31
-        readable: True
-        writable: True
+          - name: "Bits 31_16"
+            long_name: "Intercept writes of CR0–15, respectively" 
+            lsb: 16
+            msb: 31
+            readable: True
+            writable: True

data/amd/register/vmcb/004h.yml

@@ -0,0 +1,37 @@
+- name: 004h
+  long_name: "004h (vector 1)"
+  purpose: |
+      "
+      004h
+      "
+  size: 32 
+  arch: amd64
+
+  access_mechanisms:
+      - name: read
+        offset: 0x004
+        component: vmcb
+
+      - name: write
+        offset: 0x004
+        component: vmcb
+
+  fieldsets:
+    - name: latest
+      condition: "Fieldset valid on latest version of the AMD architecture"
+      size: 32
+
+      fields:
+          - name: "Bits 15_0"
+            long_name: "Intercept reads of DR0–15, respectively" 
+            lsb: 0
+            msb: 15
+            readable: True
+            writable: True
+
+          - name: "Bits 31_16"
+            long_name: "Intercept writes of DR0–15, respectively" 
+            lsb: 16
+            msb: 31
+            readable: True
+            writable: True

data/amd/register/vmcb/008h.yml

@@ -0,0 +1,32 @@
+- name: 008h
+  long_name: "008h (vector 2)"
+  purpose: |
+      "
+      008h
+      
+      Intercept exception vectors 0–31, respectively.
+      "
+  size: 32 
+  arch: amd64
+
+  access_mechanisms:
+      - name: read
+        offset: 0x008
+        component: vmcb
+
+      - name: write
+        offset: 0x008
+        component: vmcb
+
+  fieldsets:
+    - name: latest
+      condition: "Fieldset valid on latest version of the AMD architecture"
+      size: 32
+
+      fields:
+          - name: "Bits 31_0"
+            long_name: "Intercept exception vectors 0–31, respectively." 
+            lsb: 0
+            msb: 31
+            readable: True
+            writable: True

data/amd/register/vmcb/00Ch.yml

@@ -0,0 +1,249 @@
+- name: 00Ch
+  long_name: "00Ch (vector 3)"
+  purpose: |
+      "
+      00Ch (vector 3)
+      "
+  size: 32 
+  arch: amd64
+
+  access_mechanisms:
+      - name: read
+        offset: 0x00C
+        component: vmcb
+
+      - name: write
+        offset: 0x00C
+        component: vmcb
+
+  fieldsets:
+    - name: latest
+      condition: "Fieldset valid on latest version of the AMD architecture"
+      size: 32
+
+      fields:
+          - name: "Bits 0"
+            long_name: "Intercept INTR (physical maskable interrupt)." 
+            lsb: 0
+            msb: 0
+            readable: True
+            writable: True
+
+          - name: "Bits 1"
+            long_name: "Intercept NMI." 
+            lsb: 1
+            msb: 1
+            readable: True
+            writable: True
+
+          - name: "Bits 2"
+            long_name: "Intercept SMI." 
+            lsb: 2
+            msb: 2
+            readable: True
+            writable: True
+
+          - name: "Bits 3"
+            long_name: "Intercept INIT." 
+            lsb: 3
+            msb: 3
+            readable: True
+            writable: True
+
+          - name: "Bits 4"
+            long_name: "Intercept VINTR (virtual maskable interrupt)." 
+            lsb: 4
+            msb: 4
+            readable: True
+            writable: 
+
+          - name: "Bits 5"
+            long_name: "Intercept CR0 writes that change bits other than CR0.TS or CR0.MP." 
+            lsb: 5
+            msb: 5
+            readable: True
+            writable: True
+
+          - name: "Bits 6"
+            long_name: "Intercept reads of IDTR." 
+            lsb: 6
+            msb: 6
+            readable: True
+            writable: True
+
+          - name: "Bits 7"
+            long_name: "Intercept reads of GDTR." 
+            lsb: 7
+            msb: 7
+            readable: True
+            writable: True
+
+          - name: "Bits 8"
+            long_name: "Intercept reads of LDTR." 
+            lsb: 8
+            msb: 8
+            readable: True
+            writable: True
+
+          - name: "Bits 9"
+            long_name: "Intercept reads of TR" 
+            lsb: 9
+            msb: 9
+            readable: True
+            writable: True
+
+          - name: "Bits 10"
+            long_name: "Intercept writes of IDTR." 
+            lsb: 10
+            msb: 10
+            readable: True
+            writable: True
+
+          - name: "Bits 11"
+            long_name: "Intercept writes of GDTR." 
+            lsb: 11
+            msb: 11
+            readable: True
+            writable: True
+
+          - name: "Bits 12"
+            long_name: "Intercept writes of LDTR." 
+            lsb: 12
+            msb: 12
+            readable: True
+            writable: True
+
+          - name: "Bits 13"
+            long_name: "Intercept writes of TR." 
+            lsb: 13
+            msb: 13
+            readable: True
+            writable: True
+
+          - name: "Bits 14"
+            long_name: "Intercept RDTSC instruction." 
+            lsb: 14
+            msb: 14
+            readable: True
+            writable: True
+
+          - name: "Bits 15"
+            long_name: "Intercept RDPMC instruction." 
+            lsb: 15
+            msb: 15
+            readable: True
+            writable: True
+
+          - name: "Bits 16"
+            long_name: "Intercept PUSHF instruction." 
+            lsb: 16
+            msb: 16
+            readable: True
+            writable: True
+
+          - name: "Bits 17"
+            long_name: "Intercept POPF instruction" 
+            lsb: 17
+            msb: 17
+            readable: True
+            writable: True
+
+          - name: "Bits 18"
+            long_name: "Intercept CPUID instruction." 
+            lsb: 18
+            msb: 18
+            readable: True
+            writable: True
+
+          - name: "Bits 19"
+            long_name: "Intercept RSM instruction." 
+            lsb: 19
+            msb: 19
+            readable: True
+            writable: True
+
+          - name: "Bits 20"
+            long_name: "Intercept IRET instruction." 
+            lsb: 20
+            msb: 20
+            readable: True
+            writable: True
+
+          - name: "Bits 21"
+            long_name: "Intercept INTn instruction." 
+            lsb: 21
+            msb: 21
+            readable: True
+            writable: True
+
+          - name: "Bits 22"
+            long_name: "Intercept INVD instruction." 
+            lsb: 22
+            msb: 22
+            readable: True
+            writable: True
+
+          - name: "Bits 23"
+            long_name: "Intercept PAUSE instruction." 
+            lsb: 23
+            msb: 23
+            readable: True
+            writable: True
+
+          - name: "Bits 24"
+            long_name: "Intercept HLT instruction." 
+            lsb: 24
+            msb: 24
+            readable: True
+            writable: True
+
+          - name: "Bits 25"
+            long_name: "Intercept INVLPG instruction." 
+            lsb: 25
+            msb: 25
+            readable: True
+            writable: True
+
+          - name: "Bits 26"
+            long_name: "Intercept INVLPGA instruction." 
+            lsb: 26
+            msb: 26
+            readable: True
+            writable: True
+
+          - name: "Bits 27"
+            long_name: "IOIO_PROT—Intercept IN/OUT accesses to selected ports." 
+            lsb: 27
+            msb: 27
+            readable: True
+            writable: True
+
+          - name: "Bits 28"
+            long_name: "MSR_PROT—intercept RDMSR or WRMSR accesses to selected MSRs." 
+            lsb: 28
+            msb: 28
+            readable: True
+            writable: True
+
+          - name: "Bits 29"
+            long_name: "Intercept task switches." 
+            lsb: 29
+            msb: 29
+            readable: True
+            writable: True
+
+          - name: "Bits 30"
+            long_name: "FERR_FREEZE: intercept processor “freezing” during legacy FERR handling." 
+            lsb: 30
+            msb: 30
+            readable: True
+            writable: True
+
+          - name: "Bits 31"
+            long_name: "Intercept shutdown events." 
+            lsb: 31
+            msb: 31
+            readable: True
+            writable: True
+
+