Merge pull request #163 from coreboot/main

[pull] main from coreboot:main

Makefile.mk

@@ -99,7 +99,7 @@ PHONY+= clean-abuild coreboot check-style build_complete
 # site-local Makefile.mk must go first to override default locations (for binaries etc.)
 subdirs-y := site-local
 
-subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
+subdirs-y += src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
 subdirs-$(CONFIG_EC_ACPI) += src/ec/intel
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))

src/acpi/acpi.c

@@ -1489,6 +1489,16 @@ unsigned long write_acpi_tables(const unsigned long start)
 		current = fw;
 		current = acpi_align_current(current);
 		if (rsdp->xsdt_address == 0) {
+			acpi_rsdt_t *existing_rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address;
+
+			/*
+			 * Qemu only provides a smaller ACPI 1.0 RSDP, thus
+			 * allocate a bigger ACPI 2.0 RSDP structure.
+			 */
+			rsdp = (acpi_rsdp_t *)current;
+			current += sizeof(acpi_rsdp_t);
+			coreboot_rsdp = (uintptr_t)rsdp;
+
 			xsdt = (acpi_xsdt_t *)current;
 			current += sizeof(acpi_xsdt_t);
 			current = acpi_align_current(current);
@@ -1497,7 +1507,6 @@ unsigned long write_acpi_tables(const unsigned long start)
 			 * Qemu only creates an RSDT.
 			 * Add an XSDT based on the existing RSDT entries.
 			 */
-			acpi_rsdt_t *existing_rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address;
 			acpi_write_rsdp(rsdp, existing_rsdt, xsdt, oem_id);
 			acpi_write_xsdt(xsdt, oem_id, oem_table_id);
 			/*
@@ -1537,7 +1546,7 @@ unsigned long write_acpi_tables(const unsigned long start)
 
 		acpi_add_table(rsdp, ssdt);
 
-		return fw;
+		return current;
 	}
 
 	dsdt_file = cbfs_map(CONFIG_CBFS_PREFIX "/dsdt.aml", &dsdt_size);

src/acpi/acpigen_ps2_keybd.c

@@ -57,6 +57,8 @@ static const uint32_t action_keymaps[] = {
 	[PS2_KEY_KBD_BKLIGHT_TOGGLE] = KEYMAP(0x9e, KEY_KBDILLUMTOGGLE),	/* e01e */
 	[PS2_KEY_MENU] = KEYMAP(0xdd, KEY_CONTROLPANEL),	/* e0d5 */
 	[PS2_KEY_DICTATE] = KEYMAP(0xa7, KEY_DICTATE),		/* e027*/
+	[PS2_KEY_ACCESSIBILITY] = KEYMAP(0xa9, KEY_ACCESSIBILITY),	/* e029 */
+	[PS2_KEY_DO_NOT_DISTURB] = KEYMAP(0xa8, KEY_DO_NOT_DISTURB),	/* e028 */
 };
 
 /* Keymap for numeric keypad keys */

src/ec/google/chromeec/ec_acpi.c

@@ -234,6 +234,8 @@ static const enum ps2_action_key ps2_enum_val[] = {
 	[TK_MICMUTE] = PS2_KEY_MICMUTE,
 	[TK_MENU] = PS2_KEY_MENU,
 	[TK_DICTATE] = PS2_KEY_DICTATE,
+	[TK_ACCESSIBILITY] = PS2_KEY_ACCESSIBILITY,
+	[TK_DONOTDISTURB] = PS2_KEY_DO_NOT_DISTURB,
 };
 
 static void fill_ssdt_ps2_keyboard(const struct device *dev)

src/include/acpi/acpigen_ps2_keybd.h

@@ -28,6 +28,8 @@ enum ps2_action_key {
 	PS2_KEY_MICMUTE,
 	PS2_KEY_MENU,
 	PS2_KEY_DICTATE,
+	PS2_KEY_ACCESSIBILITY,
+	PS2_KEY_DO_NOT_DISTURB,
 };
 
 #define PS2_MIN_TOP_ROW_KEYS		2

src/mainboard/51nb/x210/devicetree.cb

@@ -44,8 +44,6 @@ chip soc/intel/skylake
 	register "SataPortsDevSlp[2]" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
@@ -100,7 +98,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end

src/mainboard/acer/aspire_vn7_572g/devicetree.cb

@@ -32,7 +32,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2]	= PchSerialIoSkipInit,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x1025 0x1037 inherit
 		device ref system_agent	on
@@ -244,7 +243,6 @@ chip soc/intel/skylake
 		end
 		device ref heci1	on	end
 		device ref sata		on
-			register "SataMode" = "SATA_AHCI"
 			register "SataSalpSupport" = "1"
 			register "SataPortsEnable[1]" = "1"	# HDD; BIT1 in 92h-93h
 			register "SataPortsEnable[2]" = "1"	# ODD; BIT2 in 92h-93h

src/mainboard/asrock/h110m/devicetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent	on
 			subsystemid 0x1849 0x191f

src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb

@@ -35,14 +35,12 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x1558 0x1313 inherit
 		device ref system_agent	on	end
 		device ref igpu 	on	end
 		device ref sa_thermal	on	end
 		device ref south_xhci	on
-			register "SsicPortEnable" = "0"
 			# USB2
 			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A, right
 			register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# 3G / LTE
@@ -60,7 +58,6 @@ chip soc/intel/skylake
 		device ref thermal	on	end
 		device ref heci1	on	end
 		device ref sata		on
-			register "SataSalpSupport" = "0"
 			# Ports
 			register "SataPortsEnable[0]" = "1"
 			register "SataPortsEnable[2]" = "1"

src/mainboard/facebook/monolith/devicetree.cb

@@ -40,13 +40,6 @@ chip soc/intel/skylake
 	register "SataSalpSupport" = "1"
 	register "SataPortsEnable" = "{
 		[0] = 1,
-		[1] = 0,
-		[2] = 0,
-		[3] = 0,
-		[4] = 0,
-		[5] = 0,
-		[6] = 0,
-		[7] = 0,
 	}"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
@@ -197,8 +190,6 @@ chip soc/intel/skylake
 		[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB-C Port 1 */
 	}"
 
-	register "SsicPortEnable" = "0"
-
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
@@ -214,7 +205,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoDisabled,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end

src/mainboard/google/brox/variants/baseboard/brox/ramstage.c

@@ -5,44 +5,163 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <drivers/intel/dptf/chip.h>
+#include <ec/google/chromeec/ec.h>
 #include <intelblocks/power_limit.h>
 #include <soc/pci_devs.h>
 
 
 WEAK_DEV_PTR(dptf_policy);
 
+#define SET_PSYSPL2(e, w) ((e) * (w) / 100)
+#define SET_PL2(e, w) ((e - 27) * (w) / 100)
+
+static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries,
+					size_t *intel_idx, size_t *brox_idx)
+{
+	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+	u8 tdp = get_cpu_tdp();
+	size_t i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (mchid == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) {
+			*intel_idx = cpuid_to_adl[i].limits;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(cpuid_to_adl)) {
+		printk(BIOS_ERR, "Cannot find correct intel sku index (mchid = %u).\n", mchid);
+		return false;
+	}
+
+	for (i = 0; i < num_entries; i++) {
+		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
+			*brox_idx = i;
+			break;
+		}
+	}
+
+	if (i == num_entries) {
+		printk(BIOS_ERR, "Cannot find correct brox sku index (mchid = %u).\n", mchid);
+		return false;
+	}
+
+	return true;
+}
+
 void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
 {
+	const struct device *policy_dev;
+	size_t intel_idx, brox_idx;
+	struct drivers_intel_dptf_config *config;
+	struct dptf_power_limits *settings;
+	config_t *conf;
+	struct soc_power_limits_config *soc_config;
+
 	if (!num_entries)
 		return;
 
-	const struct device *policy_dev = DEV_PTR(dptf_policy);
+	policy_dev = DEV_PTR(dptf_policy);
 	if (!policy_dev)
 		return;
 
-	struct drivers_intel_dptf_config *config = policy_dev->chip_info;
+	if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx))
+		return;
 
-	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+	config = policy_dev->chip_info;
+	settings = &config->controls.power_limits;
+	conf = config_of_soc();
+	soc_config = &conf->power_limits_config[intel_idx];
+	settings->pl1.min_power = limits[brox_idx].pl1_min_power;
+	settings->pl1.max_power = limits[brox_idx].pl1_max_power;
+	settings->pl2.min_power = limits[brox_idx].pl2_min_power;
+	settings->pl2.max_power = limits[brox_idx].pl2_max_power;
 
-	u8 tdp = get_cpu_tdp();
+	if (soc_config->tdp_pl2_override != 0) {
+		settings->pl2.max_power = soc_config->tdp_pl2_override * 1000;
+		settings->pl2.min_power = settings->pl2.max_power;
+	}
 
-	for (size_t i = 0; i < num_entries; i++) {
-		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
-			struct dptf_power_limits *settings = &config->controls.power_limits;
-			config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
-			settings->pl1.min_power = limits[i].pl1_min_power;
-			settings->pl1.max_power = limits[i].pl1_max_power;
-			settings->pl2.min_power = limits[i].pl2_min_power;
-			settings->pl2.max_power = limits[i].pl2_max_power;
-			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
-							   MILLIWATTS_TO_WATTS);
-			printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
-					limits[i].pl1_min_power,
-					limits[i].pl1_max_power,
-					limits[i].pl2_min_power,
-					limits[i].pl2_max_power,
-					limits[i].pl4_power);
-		}
+	if (soc_config->tdp_pl4 == 0)
+		soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power,
+						MILLIWATTS_TO_WATTS);
+}
+
+/*
+ * Psys calculations
+ *
+ * We use the following:
+ *
+ * For USB C charger (Max Power):
+ * +-------------+-----+------+---------+-------+
+ * | Max Power(W)| TDP | PL2  | PsysPL2 | PL3/4 |
+ * +-------------+-----+------+---------+-------+
+ * |     30      |  15 |  17  |   25    |  25   | <--- not working yet
+ * |     45      |  15 |  26  |   38    |  38   |
+ * |     60      |  15 |  35  |   51    |  51   |
+ * |    110      |  15 |  55  |   94    |  96   |
+ * +-------------+-----+------+---------+-------+
+ */
+void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
+				      const struct system_power_limits *sys_limits,
+				      size_t num_entries,
+				      const struct psys_config *config_psys)
+{
+	struct soc_power_limits_config *soc_config;
+	size_t intel_idx, brox_idx;
+	u16 volts_mv, current_ma;
+	enum usb_chg_type type;
+	u32 pl2;
+	u32 psyspl2 = 0;
+	u32 psyspl3 = 0;
+	u32 pl2_default;
+	config_t *conf;
+	u32 watts = 0;
+	int rv;
+
+	if (!num_entries)
+		return;
+
+	if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx))
+		return;
+
+	conf = config_of_soc();
+	soc_config = &conf->power_limits_config[intel_idx];
+
+	pl2_default = DIV_ROUND_UP(limits[brox_idx].pl2_max_power, MILLIWATTS_TO_WATTS);
+
+	/* Get AC adapter power */
+	rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
+
+	if (rv == 0 && type == USB_CHG_TYPE_PD) {
+		/* Detected USB-PD. Get max value of adapter */
+		watts = ((u32)current_ma * volts_mv) / 1000000;
 	}
+	/* If battery is present and has enough charge, add discharge rate */
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_battery_present_and_above_critical_threshold()) {
+		watts += 65;
+	}
+
+	/* We did not detect a battery or a Type-C charger */
+	if (watts == 0) {
+		return;
+	}
+
+	/* set psyspl2 to efficiency% of adapter rating */
+	psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts);
+	psyspl3 = psyspl2;
+	if (watts > 60)
+		psyspl3 += 2;
+
+	/* Limit PL2 if the adapter is with lower capability */
+	pl2 = (psyspl2 > pl2_default) ? pl2_default : SET_PL2(config_psys->efficiency, watts);
+
+	/* If PL4 > psyspl3, lower it */
+	if (soc_config->tdp_pl4 > psyspl3)
+		soc_config->tdp_pl4 = psyspl3;
+
+	/* now that we're done calculating, set everything */
+	soc_config->tdp_pl2_override = pl2;
+	soc_config->tdp_psyspl2 = psyspl2;
+	soc_config->tdp_psyspl3 = psyspl3;
 }

src/mainboard/google/brox/variants/brox/overridetree.cb

@@ -133,7 +133,7 @@ chip soc/intel/alderlake
 				register "options.fan.fine_grained_control" = "1"
 				register "options.fan.step_size" = "2"
 
-				device generic 0 on end
+				device generic 0 alias dptf_policy on end
 			end
 		end # DTT
 		device ref igpu on