Merge pull request #191 from coreboot/main

[pull] main from coreboot:main

Documentation/community/code_of_conduct.md

@@ -86,15 +86,25 @@ organizers may take any action they deem appropriate, up to and including
 a temporary ban or permanent expulsion from the community without warning
 (and without refund in the case of a paid event).
 
-Community organizers can be members of the arbitration team, or organizers
-of events and online communities.
+As a part of running the project, coreboot leadership has the right to
+revoke privileges as they see fit. This is not done lightly. Over the
+history of the coreboot project, there have been only a handful of times
+where an action needed to be taken.
+
+Community organizers can be members of the arbitration team, the
+leadership board, or organizers of events and online communities.
 
 ## Addressing Grievances
 
 If you feel you have been falsely or unfairly accused of violating this
 Code of Conduct, you should notify the arbitration team with a concise
 description of your grievance.
 
+Discussions about these actions are not done publicly, for obvious
+reasons. If someone believes that the circumstances that led to an
+action have changed, please send an email to all the members of the
+arbitration team and/or leadership board for discussion.
+
 ## Legal action
 
 Threatening or starting legal action against the project, sibling
@@ -115,11 +125,18 @@ communications pertaining to community business.
 
 ## Contact info
 
-Our arbitration team consists of the following people
-* Stefan Reinauer <stefan.reinauer@coreboot.org> (USA)
+Our arbitration team currently consists of the following people
+* Daniel Pono Takamori <pono@sfconservancy.org> (USA)
 * Ronald Minnich <[email protected]> (USA)
 * Martin Roth <[email protected]> (USA)
 
+If you have an issue with someone on the arbitration team, please reach
+out to the coreboot leadership board directly.
+
+The leadership board's information can be found on the
+[coreboot Leadership and Admin Boards](https://coreboot.org/leadership.html)
+page on the website.
+
 ## License and attribution
 
 This Code of Conduct is distributed under

Documentation/soc/amd/family17h.md

@@ -254,6 +254,6 @@ for AMD Family 17h Processors* (PID #55758) and *AMD Platform
 Security Processor BIOS Architecture Design Guide* (PID #54267) for
 earlier products
 2. [PSP Integration](psp_integration.md)
-3. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf)
+3. [AGESA Interface Specification for Arch2008](https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/44065_Arch2008.pdf)
 4. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso)
 5. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html)

Documentation/soc/intel/xeon_sp/community_preview_guide.md

@@ -19,6 +19,90 @@ The supported platform status are as below,
 
 - Buildable and bootable with real FSP headers/binaries
 
+## Targeted features list
+
+1. ACPI
+
+- RSDP/RSDT/XSDT/FADT/FACS/DSDT/SSDT
+
+- MCFG/MADT/SRAT/SLIT/HMAT/DMAR/CEDT
+
+- HEPT/SPMI/TPM2
+
+- HEST/EINJ/ERST/BERT
+
+2. SMBIOS
+
+- Type 0 - BIOS information
+
+- Type 1 - system information
+
+- Type 2 - base board information
+
+- Type 3 - chassis information
+
+- Type 4 - processor information
+
+- Type 17 - memory device
+
+3. Hardware related
+
+- Basic PCIe support
+
+  * IIO bifurcation
+
+  * PCIe hot plug
+
+  * VT-d
+
+- Customizable PCIe host bridge bus/MMIO resource window size for smart NIC support
+
+  * To handle the case where a large amount of PFs/VFs will be presented under specific PCIe host bridge
+
+- On-Chip accelerator (QAT, IAA, DSA, DLB)
+
+- CXL 2.0 Type-3 memory
+
+- NUMA and sub-NUMA clustering
+
+- GPIO (with physical pins)
+
+- Virtual GPIO
+
+  * eSPI based, use BMC or CPLD to expand GPIO pin counts on PCH-less SoC
+
+- BMC support
+
+  * IPMI KCS
+
+- Power Sequence
+
+  * ACPI S0/S5
+
+  * Fast cold/warm reset
+
+- CPU OSPM
+
+  * OS native (based on intel p_state/intel_idle OS driver)
+
+- RAS
+
+  * Based on FSP2.4 FSP-SMM
+
+  * APEI support
+
+  * Memory CE/UCE (firmware first mode, e.g. MCA/eMCA)
+
+  * IIO CE/UCE (firmware first mode, e.g. DPC/eDPC)
+
+4. Firmware related
+
+- Boot to various payloads (Linux payload/TianoCore/UniversalPayload)
+
+- Enlarged CBFS (>16MB) for one or multiple cloud payloads
+
+- VPD
+
 ## Build steps
 
 ### Prepare workspace

MAINTAINERS

@@ -397,6 +397,7 @@ F:	src/mainboard/google/corsola/
 F:	src/mainboard/google/geralt/
 F:	src/mainboard/google/kukui/
 F:	src/mainboard/google/oak/
+F:	src/mainboard/google/rauru/
 
 
 

src/drivers/pc80/tpm/tis.c

@@ -286,6 +286,14 @@ static inline tpm_result_t tis_wait_valid_data(int locality)
 static inline int tis_has_valid_data(int locality)
 {
 	const u8 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID;
+
+	/*
+	 * Certain TPMs require a small delay here, as they have set
+	 * TIS_STS_VALID first and TIS_STS_DATA_AVAILABLE few clocks later.
+	 */
+	if ((tpm_read_status(locality) & has_data) == has_data)
+		return 1;
+
 	return (tpm_read_status(locality) & has_data) == has_data;
 }
 
@@ -635,14 +643,6 @@ static tpm_result_t tis_readresponse(u8 *buffer, size_t *len)
 		if (offset == expected_count)
 			break;	/* We got all we need */
 
-		/*
-		 * Certain TPMs seem to need some delay between tis_wait_valid()
-		 * and tis_has_valid_data(), or some race-condition-related
-		 * issue will occur.
-		 */
-		if (CONFIG(TPM_RDRESP_NEED_DELAY))
-			udelay(10);
-
 	} while (tis_has_valid_data(locality));
 
 	/* * Make sure we indeed read all there was. */

src/drivers/usb/acpi/chip.h

@@ -49,6 +49,7 @@ struct drivers_usb_acpi_config {
 
 	/* Intel Bluetooth */
 	bool is_intel_bluetooth;
+	bool cnvi_bt_audio_offload;
 
 	/* GPIO used to take device out of reset or to put it into reset. */
 	struct acpi_gpio reset_gpio;
@@ -87,7 +88,9 @@ struct drivers_usb_acpi_config {
 bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld);
 
 /* Intel Bluetooth */
-void acpi_device_intel_bt(unsigned int reset_gpio);
-void acpi_device_intel_bt_common(void);
+void acpi_device_intel_bt(unsigned int reset_gpio,
+			  unsigned int enable_gpio,
+			  bool audio_offload);
+void acpi_device_intel_bt_common(unsigned int enable_gpio);
 
 #endif /* __USB_ACPI_CHIP_H__ */