Merge pull request #175 from coreboot/main

[pull] main from coreboot:main

payloads/libpayload/include/x86/arch/rdtsc.h

@@ -33,9 +33,9 @@
 
 static u64 rdtsc(void)
 {
-	u64 val;
-	__asm__ __volatile__ ("rdtsc" : "=A" (val));
-	return val;
+	u32 lo, hi;
+	__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
+	return (u64)hi << 32 | lo;
 }
 
 #endif

payloads/libpayload/libc/coreboot.c

@@ -262,12 +262,14 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
 	case CBMEM_ID_MEM_CHIP_INFO:
 		info->mem_chip_base = cbmem_entry->address;
 		break;
+#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)
 	case CBMEM_ID_CSE_BP_INFO:
 		info->cse_bp_info = cbmem_entry->address;
 		break;
 	case CBMEM_ID_CSE_INFO:
 		info->cse_info = cbmem_entry->address;
 		break;
+#endif
 	default:
 		break;
 	}

src/drivers/emulation/qemu/Kconfig

@@ -11,18 +11,27 @@ config DRIVERS_EMULATION_QEMU_BOCHS
 	help
 	   VGA driver for qemu emulated vga cards supporting
 	   the bochs dispi interface.  This includes
-	   standard vga, vmware svga and qxl.  The default
-	   vga (cirrus) is *not* supported, so you have to
-	   pick another one explicitly via 'qemu -vga $card'.
+	   standard vga, vmware svga, and qxl.
 
-config DRIVERS_EMULATION_QEMU_BOCHS_XRES
-	int "bochs vga xres"
+config DRIVERS_EMULATION_QEMU_CIRRUS
+	bool "cirrus svga driver"
+	default y
+	depends on CPU_QEMU_X86
+	depends on MAINBOARD_DO_NATIVE_VGA_INIT
+	select HAVE_VGA_TEXT_FRAMEBUFFER
+	select HAVE_LINEAR_FRAMEBUFFER
+	select VGA
+	help
+	   VGA driver for qemu emulated cirrus svga card.
+
+config DRIVERS_EMULATION_QEMU_XRES
+	int "qemu vga xres"
 	default 800
 	depends on LINEAR_FRAMEBUFFER
-	depends on DRIVERS_EMULATION_QEMU_BOCHS
+	depends on DRIVERS_EMULATION_QEMU_BOCHS || DRIVERS_EMULATION_QEMU_CIRRUS
 
-config DRIVERS_EMULATION_QEMU_BOCHS_YRES
-	int "bochs vga yres"
+config DRIVERS_EMULATION_QEMU_YRES
+	int "qemu vga yres"
 	default 600
 	depends on LINEAR_FRAMEBUFFER
-	depends on DRIVERS_EMULATION_QEMU_BOCHS
+	depends on DRIVERS_EMULATION_QEMU_BOCHS || DRIVERS_EMULATION_QEMU_CIRRUS

src/drivers/emulation/qemu/Makefile.mk

@@ -6,4 +6,4 @@ postcar-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c
 ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c
 
 ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += bochs.c
-ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += cirrus.c
+ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_CIRRUS) += cirrus.c

src/drivers/emulation/qemu/bochs.c

@@ -39,8 +39,8 @@
 #define VBE_DISPI_LFB_ENABLED           0x40
 #define VBE_DISPI_NOCLEARMEM            0x80
 
-static int width  = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
-static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
+static int width  = CONFIG_DRIVERS_EMULATION_QEMU_XRES;
+static int height = CONFIG_DRIVERS_EMULATION_QEMU_YRES;
 
 static void bochs_write(struct resource *res, int index, int val)
 {

src/drivers/emulation/qemu/cirrus.c

@@ -9,8 +9,8 @@
 #include <pc80/vga_io.h>
 #include <framebuffer_info.h>
 
-static int width  = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
-static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
+static int width  = CONFIG_DRIVERS_EMULATION_QEMU_XRES;
+static int height = CONFIG_DRIVERS_EMULATION_QEMU_YRES;
 static u32 addr   = 0;
 
 enum

src/mainboard/dell/xps_8300/Kconfig

@@ -0,0 +1,35 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_DELL_XPS_8300
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_4096
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_INT15
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select USE_NATIVE_RAMINIT
+	select SUPERIO_ITE_IT8772F
+
+config MAINBOARD_DIR
+	default "dell/xps_8300"
+
+config MAINBOARD_PART_NUMBER
+	default "XPS 8300"
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+	default 60
+
+config USBDEBUG_HCD_INDEX
+	default 2
+
+config VGA_BIOS_DGPU_ID
+	default "10de,1082"
+
+config CBFS_SIZE
+	default 0x26F000
+
+endif

src/mainboard/dell/xps_8300/Kconfig.name

@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_XPS_8300
+	bool "XPS 8300"

src/mainboard/dell/xps_8300/Makefile.mk

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c

src/mainboard/dell/xps_8300/acpi/ec.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */

src/mainboard/dell/xps_8300/acpi/platform.asl

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}

src/mainboard/dell/xps_8300/acpi/superio.asl

@@ -0,0 +1,2 @@
+/* SPDX-License-Identifier: CC-PDDC */
+/* Please update the license if adding licensable material. */

src/mainboard/dell/xps_8300/board_info.txt

@@ -0,0 +1,6 @@
+Category: desktop
+ROM protocol: SPI
+ROM package: SOIC-8
+ROM socketed: n
+Flashrom support: y
+Release year: 2011

src/mainboard/dell/xps_8300/devicetree.cb

@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
+	device domain 0x0 on
+		subsystemid 0x1028 0x04aa inherit
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "docking_supported" = "0"
+			register "pcie_port_coalesce" = "1"
+
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 1, 1 },
+				{ 1, 1, 1 },
+				{ 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3510)=0x3510
+				{ 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3514)=0x3514
+				{ 1, 6, 3 },
+ 				{ 1, 6, 3 },
+				{ 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x3520)=0x3520
+				{ 1, 6, 5 },
+				{ 1, 6, 5 },
+				{ 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x352c)=0x352c
+				{ 1, 6, 6 },
+				{ 0, 6, 6 },
+			}"
+
+			device ref mei1 on end
+			device ref ehci2 on end
+			device ref pcie_rp1 on end
+			device ref pcie_rp4 on end
+			device ref pcie_rp5 on end
+			device ref ehci1 on end
+			device ref lpc on
+				register "gen1_dec" = "0x003c0a01"
+				register "spi_lvscc" = "0x2005"
+				register "spi_uvscc" = "0x2005"
+			end
+			device ref sata1 on
+				register "sata_interface_speed_support" = "0x3"
+				register "sata_port_map" = "0x1f"
+			end
+			device ref smbus on end
+		end
+		device ref host_bridge on end
+		device ref peg10 on end
+	end
+end

src/mainboard/dell/xps_8300/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+	}
+}

src/mainboard/dell/xps_8300/early_init.c

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+
+#define GPIO_DEV  PNP_DEV(0x2e, IT8772F_GPIO)
+#define MOUSE_DEV PNP_DEV(0x2e, IT8772F_KBCM)
+#define EC_DEV    PNP_DEV(0x2e, IT8772F_EC)
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0e);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+
+	/* Set up GPIOs on Super I/O. */
+	ite_ac_resume_southbridge(EC_DEV);
+	ite_reg_write(MOUSE_DEV, 0x30, 0x00); // PS/2 Mouse disable
+
+	ite_reg_write(EC_DEV, 0x30, 0x01); // Environment controller activate
+	ite_reg_write(EC_DEV, 0x60, 0x0a); // Environment controller MSB Register Base Address
+	ite_reg_write(EC_DEV, 0x61, 0x30); // Environment controller LSB Register Base Address
+	ite_reg_write(EC_DEV, 0x62, 0x0a); // PME Direct Access MSB Register Base Address
+	ite_reg_write(EC_DEV, 0x63, 0x20); // PME Direct Access LSB Register Base Address
+
+	ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO Set 1
+	ite_reg_write(GPIO_DEV, 0x26, 0xfc); // GPIO Set 2, Enable pin 7 and 8 to GPIO
+	ite_reg_write(GPIO_DEV, 0x27, 0x00); // GPIO Set 3
+	ite_reg_write(GPIO_DEV, 0x28, 0x00); // GPIO Set 4
+	ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO Set 5 and 6
+	ite_reg_write(GPIO_DEV, 0x2a, 0x00); // Special function 1
+	ite_reg_write(GPIO_DEV, 0x2b, 0x00); // Special function 2
+	ite_reg_write(GPIO_DEV, 0x2c, 0x03); // Special function 3
+	ite_reg_write(GPIO_DEV, 0x60, 0x0a); // SMI MSB Register Base Address
+	ite_reg_write(GPIO_DEV, 0x62, 0x0a); // Simple I/O MSB Register Base Address
+	ite_reg_write(GPIO_DEV, 0xb0, 0x00); // Pin set 1 polarity registers
+	ite_reg_write(GPIO_DEV, 0xb1, 0x00); // Pin set 2 polarity registers
+	ite_reg_write(GPIO_DEV, 0xb2, 0x00); // Pin set 3 polarity registers
+	ite_reg_write(GPIO_DEV, 0xb3, 0x00); // Pin set 4 polarity registers
+	ite_reg_write(GPIO_DEV, 0xb4, 0x00); // Pin set 5 polarity registers
+	ite_reg_write(GPIO_DEV, 0xb8, 0x00); // Pin set 1 int pull-up disable
+	ite_reg_write(GPIO_DEV, 0xb9, 0x00); // Pin set 1 int pull-up disable
+	ite_reg_write(GPIO_DEV, 0xba, 0x00); // Pin set 1 int pull-up disable
+	ite_reg_write(GPIO_DEV, 0xbb, 0x00); // Pin set 1 int pull-up disable
+	ite_reg_write(GPIO_DEV, 0xbc, 0x00); // Pin set 1 int pull-up disable
+	ite_reg_write(GPIO_DEV, 0xbd, 0x00); // Pin set 1 int pull-up disable
+	ite_reg_write(GPIO_DEV, 0xc0, 0x01); // Set Simple I/O functions on SI/O Set 1
+	ite_reg_write(GPIO_DEV, 0xc1, 0x0c); // Set Simple I/O functions on SI/O Set 2
+	ite_reg_write(GPIO_DEV, 0xc2, 0x00); // Set Simple I/O functions on SI/O Set 3
+	ite_reg_write(GPIO_DEV, 0xc3, 0x40); // Set Simple I/O functions on SI/O Set 4
+	ite_reg_write(GPIO_DEV, 0xc4, 0x00); // Set Simple I/O functions on SI/O Set 5
+	ite_reg_write(GPIO_DEV, 0xc8, 0x01); // Set Simple I/O Output on SI/O Set 1
+	ite_reg_write(GPIO_DEV, 0xc9, 0x0c); // Set Simple I/O Output on SI/O Set 2
+	ite_reg_write(GPIO_DEV, 0xca, 0x00); // Set Simple I/O Output on SI/O Set 3
+	ite_reg_write(GPIO_DEV, 0xcb, 0x40); // Set Simple I/O Output on SI/O Set 4
+	ite_reg_write(GPIO_DEV, 0xcc, 0x00); // Set Simple I/O Output on SI/O Set 5
+	ite_reg_write(GPIO_DEV, 0xcd, 0x00); // Set Simple I/O Output on SI/O Set 6
+	ite_reg_write(GPIO_DEV, 0xe9, 0x07); // GPIO Bus Select Control Register
+	ite_reg_write(GPIO_DEV, 0xf6, 0x00); // Hardware Monitor Alert Beep Pin Mapping Register
+}