[pull] main from coreboot:main

Makefile

@@ -222,8 +222,7 @@ endif
 
 # The primary target needs to be here before we include the
 # other files
-
-real-all: real-target
+real-all: site-local-target real-target
 
 # must come rather early
 .SECONDARY:

Makefile.mk

@@ -90,6 +90,13 @@ show_coreboot: | files_added
 .PHONY: show_notices
 show_notices:: | show_coreboot
 
+# This rule allows the site-local makefile to run before starting the actual
+# coreboot build. It should not be used in the regular coreboot makefiles.
+# Note: This gets run after the immediate makefile code like updating the
+# submodules, but before any other targets.
+.PHONY: site-local-target
+site-local-target::
+
 #######################################################################
 # our phony targets
 PHONY+= clean-abuild coreboot check-style build_complete
@@ -528,7 +535,6 @@ CFLAGS_common += -fno-pie
 CFLAGS_common += -Wstring-compare
 ifeq ($(CONFIG_COMPILER_GCC),y)
 CFLAGS_common += -Wold-style-declaration
-CFLAGS_common += -Walloc-size
 CFLAGS_common += -Wcast-function-type
 # Don't add these GCC specific flags when running scan-build
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)

src/arch/arm64/dma.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/console.h>
 #include <stdlib.h>
 
 int dma_coherent(const void *ptr)

src/arch/arm64/smbios.c

@@ -3,7 +3,6 @@
 #include <arch/cache.h>
 #include <arch/lib_helpers.h>
 #include <arch/smc.h>
-#include <console/console.h>
 #include <smbios.h>
 #include <stdio.h>
 

src/drivers/intel/ish/ish.c

@@ -50,6 +50,9 @@ static void intel_ish_enable(struct device *dev)
 
 static void intel_ish_get_version(void)
 {
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
+		return;
+
 	struct cse_specific_info *info = cbmem_find(CBMEM_ID_CSE_INFO);
 	if (info == NULL)
 		return;

src/include/device/dram/rcd.h

@@ -5,7 +5,6 @@
 
 #include <types.h>
 #include <device/i2c_simple.h>
-#include <console/console.h>
 
 enum rcw_idx {
 	VEN_ID_L,

src/lib/bootmode.c

@@ -21,10 +21,6 @@ void gfx_set_init_done(int done)
 
 int display_init_required(void)
 {
-	/* Need display for showing splash screen. */
-	if (CONFIG(BMP_LOGO))
-		return 1;
-
 	/* For vboot, honor VB2_CONTEXT_DISPLAY_INIT. */
 	if (CONFIG(VBOOT)) {
 		/* Must always select MUST_REQUEST_DISPLAY when using this

src/mainboard/asrock/z87m_oc_formula/Kconfig

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if BOARD_ASROCK_Z87M_OC_FORMULA
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SUPERIO_NUVOTON_NCT6776
+
+config MAINBOARD_DIR
+	default "asrock/z87m_oc_formula"
+
+config MAINBOARD_PART_NUMBER
+	default "Z87M OC Formula"
+
+config USBDEBUG_HCD_INDEX
+	default 1 # This is the top-most of the two USB-3.0-Ports beneath the RJ45 jack.
+endif

src/mainboard/asrock/z87m_oc_formula/Kconfig.name

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_ASROCK_Z87M_OC_FORMULA
+	bool "Z87M OC Formula"

src/mainboard/asrock/z87m_oc_formula/Makefile.mk

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+bootblock-y += bootblock.c
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */

src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}

src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */

src/mainboard/asrock/z87m_oc_formula/board_info.txt

@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asrock.com/mb/Intel/Z87M%20OC%20Formula/
+ROM protocol: SPI
+Flashrom support: y
+ROM package: DIP-8 (2x)
+ROM socketed: y
+Release year: 2013

src/mainboard/asrock/z87m_oc_formula/bootblock.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/pch.h>
+
+/* FIXME: remove this if not needed */
+void mainboard_config_superio(void)
+{
+}

src/mainboard/asrock/z87m_oc_formula/devicetree.cb

@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/haswell
+	register "gpu_dp_c_hotplug" = "4"
+
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on
+			ops haswell_cpu_bus_ops
+		end
+	end
+	device domain 0 on
+		ops haswell_pci_domain_ops
+
+		device pci 00.0 on # Desktop Host bridge
+			subsystemid 0x1849 0x0c00
+		end
+		device pci 01.0 on # PEG
+		end
+		device pci 02.0 on # iGPU
+			subsystemid 0x1849 0x0412
+		end
+		device pci 03.0 on # Mini-HD audio
+			subsystemid 0x1849 0x0c0c
+		end
+
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "gen1_dec" = "0x000c0291"
+			register "gen2_dec" = "0x000c0241"
+			register "gen3_dec" = "0x000c0251"
+			register "gpe0_en_1" = "0x2246"
+			register "sata_port0_gen3_dtle" = "0xa"
+			register "sata_port1_gen3_dtle" = "0x2"
+			register "sata_port_map" = "0x3f"
+			device pci 14.0 on # xHCI Controller
+				subsystemid 0x1849 0x8c31
+			end
+			device pci 16.0 on	# MEI #1
+				subsystemid 0x1849 0x8c3a
+			end
+			device pci 16.1 off end	# MEI #2
+			device pci 19.0 on 	# Intel Gigabit Ethernet
+				subsystemid 0x1849 0x153b
+			end
+			device pci 1a.0 on 	# USB2 EHCI #2
+				subsystemid 0x1849 0x8c2d
+			end
+			device pci 1b.0 on 	# High Definition Audio
+				subsystemid 0x1849 0x1151
+			end
+			device pci 1c.0 on 	# RP #1
+				subsystemid 0x1849 0x8c10
+			end
+			device pci 1c.1 on 	# RP #2 mPCIe slot
+				subsystemid 0x1849 0x8c12
+			end
+			device pci 1c.2 on 	# RP #3
+			end
+			device pci 1c.3 on 	# RP #4 PCIe NVMe Controller
+			end
+			device pci 1c.4 on 	# RP #5
+			end
+			device pci 1c.5 on 	# RP #6
+			end
+			device pci 1c.6 on 	# RP #7
+			end
+			device pci 1c.7 on 	# RP #8
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x1849 0x8c26
+			end
+			device pci 1f.0 on # LPC bridge
+				subsystemid 0x1849 0x8c44
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0   off end	# Floppy
+					device pnp 2e.1   off end	# Parallel
+					device pnp 2e.2   on		# UART A
+						io  0x60 = 0x03f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3   off end	# UART B, IR
+					device pnp 2e.5   on		# PS/2 Keyboard/Mouse
+						io  0x60 = 0x0060
+						io  0x62 = 0x0064
+						irq 0x70 = 1		# + Keyboard IRQ
+						irq 0x72 = 12		# + Mouse IRQ (unused)
+					end
+					device pnp 2e.6   off end	# CIR
+					device pnp 2e.7   off end	# GPIO8
+					device pnp 2e.107 off end	# GPIO9
+					device pnp 2e.8   off end	# WDT
+					device pnp 2e.108 on		# GPIO0
+						irq 0xe0 = 0xf9		# + GPIO0 direction
+						irq 0xe1 = 0xfd		# + GPIO0 value
+					end
+					device pnp 2e.208 off end	# GPIOA
+					device pnp 2e.308 off end	# GPIO base
+					device pnp 2e.109 on		# GPIO1
+						irq 0xf0 = 0xf1		# + GPIO1 direction
+						irq 0xf1 = 0xf1		# + GPIO1 value
+					end
+					device pnp 2e.209 off end	# GPIO2
+					device pnp 2e.309 off end	# GPIO3
+					device pnp 2e.409 off end	# GPIO4
+					device pnp 2e.509 off end	# GPIO5
+					device pnp 2e.609 off end	# GPIO6
+					device pnp 2e.709 on		# GPIO7
+						irq 0xe0 = 0xff		# + GPIO7 direction
+					end
+					device pnp 2e.a   on		# ACPI
+						irq 0xe4 = 0x10		# + Power RAM in S3
+						irq 0xf0 = 0x20
+					end
+					device pnp 2e.b   on		# HWM, LED
+						irq 0x30 = 0xe1		# + Fan RPM sense pins
+						io  0x60 = 0x0290	# + HWM base address
+						irq 0x70 = 0
+					end
+					device pnp 2e.d   off end	# VID
+					device pnp 2e.e   off end	# CIR wake-up
+					device pnp 2e.f   off end	# GPIO PP/OD
+					device pnp 2e.14  off end	# SVID
+					device pnp 2e.16  off end	# Deep sleep
+					device pnp 2e.17  off end	# GPIOA
+				end
+			end
+			device pci 1f.2 on # SATA Controller (AHCI)
+				subsystemid 0x1849 0x8c02
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x1849 0x8c22
+			end
+			device pci 1f.5 off end	# SATA Controller (Legacy)
+			device pci 1f.6 off end	# Thermal
+		end
+	end
+end

src/mainboard/asrock/z87m_oc_formula/dsdt.asl

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}

src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads

@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP2,	-- DP
+      HDMI2,	-- DP
+      HDMI3,	-- HDMI
+      others => Disabled);
+
+end GMA.Mainboard;