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Merge pull request #853 from Chilledheart/bump_chromium_components_12…
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…4_6367

bump chromium components up to 124.0.6367.6
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Chilledheart authored Mar 20, 2024
2 parents d1ca106 + 1f06678 commit 79b91f9
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10 changes: 10 additions & 0 deletions debian/changelog
Original file line number Diff line number Diff line change
@@ -1,3 +1,13 @@
yass (1.7.5-1) UNRELEASED; urgency=medium

* net: add doh support

-- Chilledheart <[email protected]> Mon, 18 Mar 2024 16:31:44 +0800
yass (1.7.4-1) UNRELEASED; urgency=medium

* net: add doh support

-- Chilledheart <[email protected]> Sun, 17 Mar 2024 14:21:12 +0800
yass (1.7.3-1) UNRELEASED; urgency=medium

* c-ares: fix CVE-2024-25629
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3 changes: 2 additions & 1 deletion third_party/zlib/adler32.c
Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,8 @@ uLong ZEXPORT adler32_z(uLong adler, const Bytef *buf, z_size_t len) {
return adler | (sum2 << 16);
}

#if defined(ADLER32_SIMD_SSSE3) || defined(ADLER32_SIMD_NEON)
#if defined(ADLER32_SIMD_SSSE3) || defined(ADLER32_SIMD_NEON) \
|| defined(RISCV_RVV)
/*
* Use SIMD to compute the adler32. Since this function can be
* freely used, check CPU features here. zlib convention is to
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33 changes: 28 additions & 5 deletions third_party/zlib/cpu_features.c
Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,13 @@ int ZLIB_INTERNAL x86_cpu_enable_ssse3 = 0;
int ZLIB_INTERNAL x86_cpu_enable_simd = 0;
int ZLIB_INTERNAL x86_cpu_enable_avx512 = 0;

int ZLIB_INTERNAL riscv_cpu_enable_rvv = 0;
int ZLIB_INTERNAL riscv_cpu_enable_vclmul = 0;

#ifndef CPU_NO_SIMD

#if defined(ARMV8_OS_ANDROID) || defined(ARMV8_OS_LINUX) || defined(ARMV8_OS_FUCHSIA) || defined(ARMV8_OS_IOS)
#if defined(ARMV8_OS_ANDROID) || defined(ARMV8_OS_LINUX) || \
defined(ARMV8_OS_FUCHSIA) || defined(ARMV8_OS_IOS)
#include <pthread.h>
#endif

Expand All @@ -62,7 +66,10 @@ int ZLIB_INTERNAL x86_cpu_enable_avx512 = 0;
static void _cpu_check_features(void);
#endif

#if defined(ARMV8_OS_ANDROID) || defined(ARMV8_OS_LINUX) || defined(ARMV8_OS_MACOS) || defined(ARMV8_OS_FUCHSIA) || defined(X86_NOT_WINDOWS) || defined(ARMV8_OS_IOS)
#if defined(ARMV8_OS_ANDROID) || defined(ARMV8_OS_LINUX) || \
defined(ARMV8_OS_MACOS) || defined(ARMV8_OS_FUCHSIA) || \
defined(X86_NOT_WINDOWS) || defined(ARMV8_OS_IOS) || \
defined(RISCV_RVV)
#if !defined(ARMV8_OS_MACOS)
// _cpu_check_features() doesn't need to do anything on mac/arm since all
// features are known at build time, so don't call it.
Expand Down Expand Up @@ -143,7 +150,6 @@ BOOL InitOnceExecuteOnce(PINIT_ONCE InitOnce,
}

#endif // _WIN32_WINNT < 0x0600

static INIT_ONCE cpu_check_inited_once = INIT_ONCE_STATIC_INIT;
static BOOL CALLBACK _cpu_check_features_forwarder(PINIT_ONCE once, PVOID param, PVOID* context)
{
Expand Down Expand Up @@ -251,6 +257,23 @@ static void _cpu_check_features(void)
x86_cpu_enable_avx512 = _xgetbv(0) & 0x00000040;
#endif
}
#endif // x86 & NO_SIMD

#elif defined(RISCV_RVV)
#include <sys/auxv.h>

#ifndef ZLIB_HWCAP_RVV
#define ZLIB_HWCAP_RVV (1 << ('v' - 'a'))
#endif
#endif
#endif

/* TODO(cavalcantii)
* - add support for Android@RISCV i.e. __riscv_hwprobe().
* - detect vclmul (crypto extensions).
*/
static void _cpu_check_features(void)
{
unsigned long features = getauxval(AT_HWCAP);
riscv_cpu_enable_rvv = !!(features & ZLIB_HWCAP_RVV);
}
#endif // ARM | x86 | RISCV
#endif // NO SIMD CPU
6 changes: 4 additions & 2 deletions third_party/zlib/crc32.c
Original file line number Diff line number Diff line change
Expand Up @@ -706,7 +706,8 @@ unsigned long ZEXPORT crc32_z(unsigned long crc, const unsigned char FAR *buf,
* place to cache CPU features if needed for those later, more
* interesting crc32() calls.
*/
#if defined(CRC32_SIMD_SSE42_PCLMUL) || defined(CRC32_ARMV8_CRC32)
#if defined(CRC32_SIMD_SSE42_PCLMUL) || defined(CRC32_ARMV8_CRC32) \
|| defined(RISCV_RVV)
/*
* Since this routine can be freely used, check CPU features here.
*/
Expand Down Expand Up @@ -1085,7 +1086,8 @@ unsigned long ZEXPORT crc32(unsigned long crc, const unsigned char FAR *buf,
/* Some bots compile with optimizations disabled, others will emulate
* ARM on x86 and other weird combinations.
*/
#if defined(CRC32_SIMD_SSE42_PCLMUL) || defined(CRC32_ARMV8_CRC32)
#if defined(CRC32_SIMD_SSE42_PCLMUL) || defined(CRC32_ARMV8_CRC32) \
|| defined(RISCV_RVV)
/* We got to verify CPU features, so exploit the common usage pattern
* of calling this function with Z_NULL for an initial valid crc value.
* This allows to cache the result of the feature check and avoid extraneous
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3 changes: 2 additions & 1 deletion third_party/zlib/deflate.c
Original file line number Diff line number Diff line change
Expand Up @@ -401,7 +401,8 @@ int ZEXPORT deflateInit2_(z_streamp strm, int level, int method,
// for all wrapper formats (e.g. RAW, ZLIB, GZIP).
// Feature detection is not triggered while using RAW mode (i.e. we never
// call crc32() with a NULL buffer).
#if defined(CRC32_ARMV8_CRC32) || defined(CRC32_SIMD_SSE42_PCLMUL)
#if defined(CRC32_ARMV8_CRC32) || defined(CRC32_SIMD_SSE42_PCLMUL) \
|| defined(RISCV_RVV)
cpu_check_features();
#endif

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4 changes: 4 additions & 0 deletions yass.spec.in
Original file line number Diff line number Diff line change
Expand Up @@ -240,6 +240,10 @@ for embedded devices and low end boxes.
%systemd_postun_with_restart yass-redir.service

%changelog
* Mon Mar 18 2024 Chilledheart <[email protected]> - 1.7.5-1
- net: add doh support
* Sun Mar 17 2024 Chilledheart <[email protected]> - 1.7.4-1
- net: add doh support
* Thu Mar 7 2024 Chilledheart <[email protected]> - 1.7.3-1
- c-ares: fix CVE-2024-25629
* Thu Mar 7 2024 Chilledheart <[email protected]> - 1.7.2-1
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