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i#3044 AArch64 SVE: Add Z registers and a simple encoding group. #3073

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merged 4 commits into from
Jun 29, 2018
Merged

i#3044 AArch64 SVE: Add Z registers and a simple encoding group. #3073

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8055b80
i#3044 AArch64 SVE: Add Z registers and a simple encoding group.
fhahn Jun 9, 2018
c602352
No XZR from Z16.
fhahn Jun 28, 2018
36900d8
Fix macro indent.
fhahn Jun 28, 2018
8efb09b
Merge branch 'master' into i3044-sve-arith-unpred
fhahn Jun 29, 2018
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59 changes: 59 additions & 0 deletions core/arch/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -909,6 +909,20 @@ encode_opnd_float_reg(int pos, opnd_t opnd, OUT uint *enc_out)
return true;
}

/* Used to encode a SVE vector register (z registers). */

static inline bool
encode_opnd_z(uint pos_start, opnd_t opnd, OUT uint *enc_out)
{
uint num;
if (!opnd_is_reg(opnd))
return false;
num = opnd_get_reg(opnd) - DR_REG_Z0;
if (num >= 32)
return false;
*enc_out = num << pos_start;
return true;
}

/*******************************************************************************
* Pairs of functions for decoding and encoding each type of operand, as listed in
Expand Down Expand Up @@ -1141,6 +1155,21 @@ encode_opnd_q0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
return encode_opnd_vector_reg(0, 4, opnd, enc_out);
}

/* z0: Z register at bit position 0. */

static inline bool
decode_opnd_z0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
*opnd = opnd_create_reg(DR_REG_Z0 + extract_uint(enc, 0, 5));
return true;
}

static inline bool
encode_opnd_z0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_opnd_z(0, opnd, enc_out);
}

/* q0p1: as q0 but add 1 mod 32 to reg number */

static inline bool
Expand Down Expand Up @@ -1281,6 +1310,21 @@ encode_opnd_d5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
return encode_opnd_vector_reg(5, 3, opnd, enc_out);
}

/* z5: Z register at bit position 5. */

static inline bool
decode_opnd_z5(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
*opnd = opnd_create_reg(DR_REG_Z0 + extract_uint(enc, 5, 5));
return true;
}

static inline bool
encode_opnd_z5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_opnd_z(5, opnd, enc_out);
}

/* mem9qpost: post-indexed mem9q, so offset is zero */

static inline bool
Expand Down Expand Up @@ -1601,6 +1645,21 @@ encode_opnd_x16p1(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out
return encode_opnd_wxnp(true, 1, 16, opnd, enc_out);
}

/* z16: Z register at bit position 16. */

static inline bool
decode_opnd_z16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
*opnd = opnd_create_reg(DR_REG_Z0 + extract_uint(enc, 16, 5));
return true;
}

static inline bool
encode_opnd_z16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_opnd_z(16, opnd, enc_out);
}

/* mem9off: just the 9-bit offset from mem9 */

static inline bool
Expand Down
11 changes: 11 additions & 0 deletions core/arch/aarch64/codec.txt
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Expand Up @@ -69,6 +69,7 @@
---------------------------xxxxx s0 # S register
---------------------------xxxxx d0 # D register
---------------------------xxxxx q0 # Q register
---------------------------xxxxx z0 # Z register
---------------------------xxxxx q0p1 # Q register, add 1
---------------------------xxxxx q0p2 # Q register, add 2
---------------------------xxxxx q0p3 # Q register, add 3
Expand All @@ -79,6 +80,7 @@
----------------------xxxxx----- h5 # H register
----------------------xxxxx----- s5 # S register
----------------------xxxxx----- d5 # D register
----------------------xxxxx----- z5 # Z register
----------------------xxxxx----- mem9qpost # size is 16 bytes; post-index
--------------------xx---------- vmsz # B/H/S/D for load/store multiple structures
--------------------xxxx-------- imm4 # option for CLREX, DSB, DMB, ISB
Expand All @@ -101,6 +103,7 @@
-----------xxxxx---------------- x16 # X register (or XZR)
-----------xxxxx---------------- x16p0 # even-numbered X register (or XZR)
-----------xxxxx---------------- x16p1 # ... add 1
-----------xxxxx---------------- z16 # Z register
-----------xxxxxxxxx------------ mem9off # immed offset for mem9/mem9post
-----------xxxxxxxxx--xxxxx----- mem9q # size is 16 bytes
-----------xxxxxxxxx--xxxxx----- prf9 # size is 0 bytes (prefetch variant of mem9)
Expand Down Expand Up @@ -1110,3 +1113,11 @@ x101101011000000000101xxxxxxxxxx cls wx0 : wx5
00011111xx0xxxxx1xxxxxxxxxxxxxxx fmsub float_reg0 : float_reg5 float_reg16 float_reg10
00011111xx1xxxxx0xxxxxxxxxxxxxxx fnmadd float_reg0 : float_reg5 float_reg16 float_reg10
00011111xx1xxxxx1xxxxxxxxxxxxxxx fnmsub float_reg0 : float_reg5 float_reg16 float_reg10

# SVE integer add/subtract vectors (unpredicated)
00000100xx1xxxxx000000xxxxxxxxxx add z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000001xxxxxxxxxx sub z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000100xxxxxxxxxx sqadd z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000101xxxxxxxxxx uqadd z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000110xxxxxxxxxx sqsub z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000111xxxxxxxxxx uqsub z0 : z5 z16 bhsd_sz
4 changes: 4 additions & 0 deletions core/arch/aarch64/encode.c
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Expand Up @@ -75,6 +75,10 @@ const char * const reg_names[] = {
"b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
"b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
"b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
"z0", "z1", "z2", "q3", "z4", "z5", "z6", "z7",
"z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15",
"z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"nzcv", "fpcr", "fpsr",
"tpidr_el0", "tpidrro_el0"
};
Expand Down
6 changes: 5 additions & 1 deletion core/arch/aarch64/instr_create.h
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Expand Up @@ -617,7 +617,11 @@
#define INSTR_CREATE_fmov_general(dc, Rd, Rn) \
instr_create_1dst_1src(dc, OP_fmov, Rd, Rn)

/* -------- Advanced SIMD three same including fp16 versions ---------------- */
/* -------- Advanced SIMD three same including fp16 versions ----------------
* Some macros are also used for
* SVE Integer Arithmetic - Unpredicated Group
* Advanced SIMD three same (FP16)
*/

/**
* Creates a SHADD vector instruction.
Expand Down
1 change: 1 addition & 0 deletions core/arch/decode.h
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Expand Up @@ -321,6 +321,7 @@ enum {
OPSZ_120, /**< 120 bytes. Needed for load/store of register lists. */
OPSZ_124, /**< 124 bytes. Needed for load/store of register lists. */
OPSZ_128, /**< 128 bytes. Needed for load/store of register lists. */
OPSZ_SCALABLE, /** Scalable size for SVE vector registers. */
#ifdef AVOID_API_EXPORT
/* Add new size here. Also update size_names[] in decode_shared.c along with
* the size routines in opnd_shared.c.
Expand Down
1 change: 1 addition & 0 deletions core/arch/decode_shared.c
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Expand Up @@ -213,6 +213,7 @@ const char * const size_names[] = {
"OPSZ_120",
"OPSZ_124",
"OPSZ_128",
"OPSZ_SCALABLE",
"OPSZ_1_of_4",
"OPSZ_2_of_4",
"OPSZ_1_of_8",
Expand Down
12 changes: 12 additions & 0 deletions core/arch/opnd.h
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Expand Up @@ -262,6 +262,18 @@ enum {
DR_REG_B24, DR_REG_B25, DR_REG_B26, DR_REG_B27,
DR_REG_B28, DR_REG_B29, DR_REG_B30, DR_REG_B31,

# ifdef AARCH64
/* SVE vector registers */
DR_REG_Z0, DR_REG_Z1, DR_REG_Z2, DR_REG_Z3,
DR_REG_Z4, DR_REG_Z5, DR_REG_Z6, DR_REG_Z7,
DR_REG_Z8, DR_REG_Z9, DR_REG_Z10, DR_REG_Z11,
DR_REG_Z12, DR_REG_Z13, DR_REG_Z14, DR_REG_Z15,
DR_REG_Z16, DR_REG_Z17, DR_REG_Z18, DR_REG_Z19,
DR_REG_Z20, DR_REG_Z21, DR_REG_Z22, DR_REG_Z23,
DR_REG_Z24, DR_REG_Z25, DR_REG_Z26, DR_REG_Z27,
DR_REG_Z28, DR_REG_Z29, DR_REG_Z30, DR_REG_Z31,
# endif

# ifndef AARCH64
/* Coprocessor registers */
DR_REG_CR0, DR_REG_CR1, DR_REG_CR2, DR_REG_CR3,
Expand Down
2 changes: 2 additions & 0 deletions core/arch/opnd_shared.c
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Expand Up @@ -2182,6 +2182,8 @@ reg_get_size(reg_id_t reg)
return OPSZ_8;
if (reg == DR_REG_WZR)
return OPSZ_4;
if (reg >= DR_REG_Z0 && reg <= DR_REG_Z31)
return OPSZ_SCALABLE;
# endif
if (reg == DR_REG_TPIDRURW || reg == DR_REG_TPIDRURO)
return OPSZ_PTR;
Expand Down
26 changes: 26 additions & 0 deletions suite/tests/api/dis-a64.txt
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Expand Up @@ -2075,3 +2075,29 @@ fd7fffff : ldr d31, [sp,#32760] : ldr +0x7ff8(%sp)[8byte] -> %d31
1f7789e4 : fnmsub d4, d15, d23, d2 : fnmsub %d15 %d23 %d2 -> %d4
1f3789e4 : fnmsub s4, s15, s23, s2 : fnmsub %s15 %s23 %s2 -> %s4
1ff789e4 : fnmsub h4, h15, h23, h2 : fnmsub %h15 %h23 %h2 -> %h4

# SVE integer add/subtract vectors (unpredicated)
043e0362 : add z2.b, z27.b, z30.b : add %z27 %z30 $0x00 -> %z2
047e0362 : add z2.h, z27.h, z30.h : add %z27 %z30 $0x01 -> %z2
04be0362 : add z2.s, z27.s, z30.s : add %z27 %z30 $0x02 -> %z2
04fe0362 : add z2.d, z27.d, z30.d : add %z27 %z30 $0x03 -> %z2
043d05a0 : sub z0.b, z13.b, z29.b : sub %z13 %z29 $0x00 -> %z0
047d05a0 : sub z0.h, z13.h, z29.h : sub %z13 %z29 $0x01 -> %z0
04bd05a0 : sub z0.s, z13.s, z29.s : sub %z13 %z29 $0x02 -> %z0
04fd05a0 : sub z0.d, z13.d, z29.d : sub %z13 %z29 $0x03 -> %z0
042a123f : sqadd z31.b, z17.b, z10.b : sqadd %z17 %z10 $0x00 -> %z31
046a123f : sqadd z31.h, z17.h, z10.h : sqadd %z17 %z10 $0x01 -> %z31
04aa123f : sqadd z31.s, z17.s, z10.s : sqadd %z17 %z10 $0x02 -> %z31
04ea123f : sqadd z31.d, z17.d, z10.d : sqadd %z17 %z10 $0x03 -> %z31
043417e2 : uqadd z2.b, z31.b, z20.b : uqadd %z31 %z20 $0x00 -> %z2
047417e2 : uqadd z2.h, z31.h, z20.h : uqadd %z31 %z20 $0x01 -> %z2
04b417e2 : uqadd z2.s, z31.s, z20.s : uqadd %z31 %z20 $0x02 -> %z2
04f417e2 : uqadd z2.d, z31.d, z20.d : uqadd %z31 %z20 $0x03 -> %z2
043719e4 : sqsub z4.b, z15.b, z23.b : sqsub %z15 %z23 $0x00 -> %z4
047719e4 : sqsub z4.h, z15.h, z23.h : sqsub %z15 %z23 $0x01 -> %z4
04b719e4 : sqsub z4.s, z15.s, z23.s : sqsub %z15 %z23 $0x02 -> %z4
04f719e4 : sqsub z4.d, z15.d, z23.d : sqsub %z15 %z23 $0x03 -> %z4
04281f42 : uqsub z2.b, z26.b, z8.b : uqsub %z26 %z8 $0x00 -> %z2
04681f42 : uqsub z2.h, z26.h, z8.h : uqsub %z26 %z8 $0x01 -> %z2
04a81f42 : uqsub z2.s, z26.s, z8.s : uqsub %z26 %z8 $0x02 -> %z2
04e81f42 : uqsub z2.d, z26.d, z8.d : uqsub %z26 %z8 $0x03 -> %z2
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