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i#2440: Macros for creating conditional instructions #4500
i#2440: Macros for creating conditional instructions #4500
Commits on Oct 29, 2020
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i#2440: Macros for creating conditional instructions
Add macros to create conditional instructions Add functions conidtional predicate operands Add tests to verify the added functiononality
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Commits on Nov 2, 2020
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i#1569 AArch64: Enable -steal_reg_at_reset for AArch64 (#4503)
Enables the diagnostic option -steal_reg_at_reset for AArch64, generalizing the existing ARM code. Switches -reset_at_fragment_count to work in release build by using the sum of the release stats num_bbs and num_traces. Adds a release-build syslog for an informational notification when any reset occurs. Adds a test of -steal_reg_at_reset. Includes the key fix for #4497 since it could show up on the new test or with use of this now-enabled option; the full fix for that with better tests for its code path will come in separately. Issue: #1569, #4497
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Optimise mcontext init by avoiding excessive zeroing. (#4499)
Instead of using partial struct initialisation, initialise the required fields individually. We've found that the time taken to zero a large struct shows up as noticeable overhead for optimised clients. So, instead of using partial struct initialisation, we set the fields required individually.
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i#1369: Use synch flush callback to enable drcachesim tracing. (#4491)
DR translates a fault in the code cache to a fault at the corresponding application address. This is done using ilist reconstruction for the fragment where the fault occurred. But, this does not work as expected when the DR client changes instrumentation during execution; currently, drcachesim does this to enable tracing after -trace_after_instrs. The reconstructed basic block gets the new instrumentation whereas the one in code cache has the old one. This causes issues during fault handling. In the current drcachesim case, it appears as though a meta-instr has faulted because the reconstructed ilist has a meta-instr at the code cache fault pc. This issue may manifest differently if the basic block with the new instrumentation is smaller than the old one (unlike the drcachesim 'meta-instr faulted' case) and the faulting address lies beyond the end of the new instrumented basic block. We may see an ASSERT_NOT_REACHED due to the ilist walk ending before the faulting code cache pc was found in the reconstructed ilist. In the existing code, drcachesim attempts to avoid this by flushing old fragments using dr_unlink_flush_region after it switches to the tracing instrumentation. However, due to the flush being asynch, there's a race and the flush does not complete in time. This PR adds support for a callback in the synchronous dr_flush_region API. The callback is executed after the flush but before the threads are resumed. Using the dr_flush_region callback to change drcachesim instrumentation ensures that old instrumentation is not applied after the flush and the new one is not applied before. Fixes: #1369
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Add gdb scripts for memquery and drsymload (#4505)
Adds two gdb python scripts I've developed that may be useful to others: 1) drsymload: loads DR symbols regardless of gdb's current state, which may include having DR symbols at the wrong address. It does this by reading /proc/self/maps and running objdump on libdynamorio.so. Ideally this would be integrated into a revived libdynamorio.so-gdb.py: that's part of #2100. 2) memquery: prints the /proc/self/maps line for a given address. I'm still shocked gdb doesn't provide such a command natively. Issue: #2100
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Fix uninitialized var in drmemtrace offline instru (#4506)
While investigating #4460 I found that reg_ptr_used in insert_save_addr is uninitialized locally and insert_obtain_addr only writes it when true, leaving it uninitialized for the false case: thus we may re-instate the buffer pointer in cases where we don't need to. I believe this is only a performance issue. Issue: #4460
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i#2440: Remove sizes of imm operands from docstings
Change-Id: Ia3699cc5eb8074a10d8ce9e6c362c1bffd0cf477
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