i#5326: Partition AArch64 codec by ISA version

core/ir/aarch64/codec.c

@@ -1,6 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2017-2022 Google, Inc.  All rights reserved.
- * Copyright (c) 2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016-2022 ARM Limited. All rights reserved.
  * **********************************************************/
 
 /*
@@ -4855,9 +4855,22 @@ encode_opnds_tbz(byte *pc, instr_t *instr, uint enc, decode_info_t *di)
 
 /******************************************************************************/
 
-/* Include automatically generated decoder and encoder. */
-#include "decode_gen.h"
-#include "encode_gen.h"
+/* Include automatically generated decoder and encoder files. Decode and encode
+ * code is partitioned into versions of the AArch64 architecture starting with
+ * v8.0. The decode/encode logic is chained together into a pipeline with v8.0
+ * calling v8.1, which calls v8.2 and so on, returning from the decode/encode
+ * functions as soon as a match is found.
+ */
+#include "opnd_decode_funcs.h"
+#include "opnd_encode_funcs.h"
+#include "decode_gen_sve.h"
+#include "decode_gen_v82.h"
+#include "decode_gen_v81.h"
+#include "decode_gen_v80.h"
+#include "encode_gen_sve.h"
+#include "encode_gen_v82.h"
+#include "encode_gen_v81.h"
+#include "encode_gen_v80.h"
 
 /******************************************************************************/
 
@@ -4872,7 +4885,7 @@ decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr)
     CLIENT_ASSERT(instr->opcode == OP_INVALID || instr->opcode == OP_UNDECODED,
                   "decode: instr is already decoded, may need to call instr_reset()");
 
-    if (!decoder(enc, dcontext, orig_pc, instr)) {
+    if (!decoder_v80(enc, dcontext, orig_pc, instr)) {
         /* This clause handles undefined HINT instructions. See the comment
          * 'Notes on specific instructions' in codec.txt for details. If the
          * decoder reads an undefined hint, a message with the unallocated
@@ -4963,5 +4976,5 @@ uint
 encode_common(byte *pc, instr_t *i, decode_info_t *di)
 {
     ASSERT(((ptr_int_t)pc & 3) == 0);
-    return encoder(pc, i, di);
+    return encoder_v80(pc, i, di);
 }

core/ir/aarch64/codec_sve.txt

@@ -0,0 +1,52 @@
+# **********************************************************
+# Copyright (c) 2016-2022 ARM Limited. All rights reserved.
+# **********************************************************
+
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+#   this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+#   this list of conditions and the following disclaimer in the documentation
+#   and/or other materials provided with the distribution.
+#
+# * Neither the name of ARM Limited nor the names of its contributors may be
+#   used to endorse or promote products derived from this software without
+#   specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL ARM LIMITED OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+
+# This file defines instruction encodings for the Scalable Vector Extension
+# (SVE) and is a placeholder for future work. There are 1288 instructions in
+# the specification including their variants. This file is for version 1 of
+# SVE. Version 2 instructions will be defined in another codec_<version>.txt
+# file when implemented.
+
+# See header comments in codec_v80.txt and opnd_defs.txt to understand how
+# instructions are defined for the purposes of decode and encode code
+# generation.
+
+# Instruction definitions:
+
+00000100xx1xxxxx000000xxxxxxxxxx  n   9      add  z0 : z5 z16 bhsd_sz
+00000100xx011010000xxxxxxxxxxxxx  n   21     and  z0 : p10_low z0 z5 bhsd_sz
+00000100xx011011000xxxxxxxxxxxxx  n   29     bic  z0 : p10_low z0 z5 bhsd_sz
+00000100xx011001000xxxxxxxxxxxxx  n   90     eor  z0 : p10_low z0 z5 bhsd_sz
+00000100xx011000000xxxxxxxxxxxxx  n   327    orr  z0 : p10_low z0 z5 bhsd_sz
+00000100xx1xxxxx000100xxxxxxxxxx  n   403  sqadd  z0 : z5 z16 bhsd_sz
+00000100xx1xxxxx000110xxxxxxxxxx  n   425  sqsub  z0 : z5 z16 bhsd_sz
+00000100xx1xxxxx000001xxxxxxxxxx  n   470    sub  z0 : z5 z16 bhsd_sz
+00000100xx1xxxxx000101xxxxxxxxxx  n   531  uqadd  z0 : z5 z16 bhsd_sz
+00000100xx1xxxxx000111xxxxxxxxxx  n   538  uqsub  z0 : z5 z16 bhsd_sz