i#3544 RV64: Added an encoder and some fixes and improvments to the decoder

.github/workflows/ci-riscv64.yml

@@ -94,6 +94,7 @@ jobs:
         DYNAMORIO_CROSS_RISCV64_LINUX_ONLY: yes
         CI_TRIGGER: ${{ github.event_name }}
         CI_BRANCH: ${{ github.ref }}
+        QEMU_LD_PREFIX: /usr/riscv64-linux-gnu/
 
     - name: Send failure mail to dynamorio-devs
       if: failure() && github.ref == 'refs/heads/master'

api/docs/bt.dox

@@ -731,8 +731,9 @@ disassemble_from_copy(), and disassemble_to_buffer().
 
 The style of disassembly can be controlled through the
 \ref op_syntax_intel "-syntax_intel" (for Intel-style disassembly),
-\ref op_syntax_att "-syntax_att" (for AT&T-style disassembly), and
-\ref op_syntax_arm "-syntax_arm" (for ARM-style disassembly) runtime
+\ref op_syntax_att "-syntax_att" (for AT&T-style disassembly),
+\ref op_syntax_arm "-syntax_arm" (for ARM-style disassembly), and
+\ref op_syntax_riscv "-syntax_riscv" (for RISC-V-style disassembly) runtime
 options, or the disassemble_set_syntax() function.  The default disassembly
 style is DynamoRIO's custom style, which lists all operands (both implicit
 and explicit).  The sources are listed first, followed by "->", and then

api/docs/deployment.dox

@@ -920,6 +920,11 @@ they want to shrink memory usage
     ARM assembler syntax rather than the default show-implicit-operands
     syntax.  This can also be set using disassemble_set_syntax().
 
+ - \b -syntax_riscv: \anchor op_syntax_riscv
+    This option causes DynamoRIO to output all disassembly using
+    RISC-V assembler syntax rather than the default show-implicit-operands
+    syntax.  This can also be set using disassemble_set_syntax().
+
  - \b -disasm_mask:
     This option sets the disassembly style to the specified bitmask of
     dr_disasm_flags_t values.  This option overlaps with -syntax_intel,

clients/drcachesim/common/options.cpp

@@ -540,15 +540,16 @@ droption_t<bytesize_t>
                 "and the references following the simulated ones are dropped.");
 
 droption_t<std::string>
-    op_view_syntax(DROPTION_SCOPE_FRONTEND, "view_syntax", "att/arm/dr",
+    op_view_syntax(DROPTION_SCOPE_FRONTEND, "view_syntax", "att/arm/dr/riscv",
                    "Syntax to use for disassembly.",
                    "Specifies the syntax to use when viewing disassembled offline traces."
                    // TODO i#4382: Add aarch64 syntax support.
                    " The option can be set to one of \"att\" (AT&T style), \"intel\""
                    " (Intel style), \"dr\" (DynamoRIO's native style with all implicit"
-                   " operands listed), and \"arm\" (32-bit ARM style). An invalid"
-                   " specification falls back to the default, which is \"att\" for x86,"
-                   " \"arm\" for ARM (32-bit), and \"dr\" for AArch64.");
+                   " operands listed), \"arm\" (32-bit ARM style), and \"riscv\" (RISC-V "
+                   "style). An invalid specification falls back to the default, which is "
+                   "\"att\" for x86, \"arm\" for ARM (32-bit), \"dr\" for AArch64, "
+                   "and \"riscv\" for RISC-V.");
 
 droption_t<std::string>
     op_config_file(DROPTION_SCOPE_FRONTEND, "config_file", "",

clients/drcachesim/tests/view_test.cpp

@@ -105,7 +105,9 @@ class view_test_t : public view_t {
     {
         module_mapper_->get_loaded_modules();
         dr_disasm_flags_t flags =
-            IF_X86_ELSE(DR_DISASM_ATT, IF_AARCH64_ELSE(DR_DISASM_DR, DR_DISASM_ARM));
+            IF_X86_ELSE(DR_DISASM_ATT,
+                        IF_AARCH64_ELSE(DR_DISASM_DR,
+                                        IF_RISCV64_ELSE(DR_DISASM_RISCV, DR_DISASM_ARM)));
         disassemble_set_syntax(flags);
         return "";
     }

clients/drcachesim/tools/view.cpp

@@ -101,14 +101,17 @@ view_t::initialize_stream(memtrace_stream_t *serial_stream)
     std::string error = module_mapper_->get_last_error();
     if (!error.empty())
         return "Failed to load binaries: " + error;
-    dr_disasm_flags_t flags =
-        IF_X86_ELSE(DR_DISASM_ATT, IF_AARCH64_ELSE(DR_DISASM_DR, DR_DISASM_ARM));
+    dr_disasm_flags_t flags = IF_X86_ELSE(
+        DR_DISASM_ATT,
+        IF_AARCH64_ELSE(DR_DISASM_DR, IF_RISCV64_ELSE(DR_DISASM_RISCV, DR_DISASM_ARM)));
     if (knob_syntax_ == "intel") {
         flags = DR_DISASM_INTEL;
     } else if (knob_syntax_ == "dr") {
         flags = DR_DISASM_DR;
     } else if (knob_syntax_ == "arm") {
         flags = DR_DISASM_ARM;
+    } else if (knob_syntax_ == "riscv") {
+        flags = DR_DISASM_RISCV;
     }
     disassemble_set_syntax(flags);
     return "";

clients/drdisas/drdisas.cpp

@@ -67,7 +67,7 @@ droption_t<bool> op_show_bytes(DROPTION_SCOPE_FRONTEND, "show_bytes", true,
                                "Display the instruction encoding bytes.",
                                "Display the instruction encoding bytes.");
 
-#if defined(AARCH64) || defined(ARM)
+#if defined(AARCH64) || defined(ARM) || defined(RISCV64)
 #    define MAX_INSTR_LENGTH 4
 #else
 #    define MAX_INSTR_LENGTH 17
@@ -165,6 +165,10 @@ main(int argc, const char *argv[])
     }
 #endif
 
+#ifdef RISCV64
+    disassemble_set_syntax(DR_DISASM_RISCV);
+#endif
+
     // Turn the arguments into a series of hex values.
     std::vector<byte> bytes;
     for (int i = last_index; i < argc; ++i) {

core/drlibc/drlibc_module_elf.c

@@ -130,7 +130,8 @@ is_elf_so_header_common(app_pc base, size_t size, bool memory)
         ASSERT_CURIOSITY(!memory ||
 #ifdef X64
                          elf_header.e_machine == EM_X86_64 ||
-                         elf_header.e_machine == EM_AARCH64
+                         elf_header.e_machine == EM_AARCH64 ||
+                         elf_header.e_machine == EM_RISCV
 #else
                          elf_header.e_machine == EM_386 || elf_header.e_machine == EM_ARM
 #endif

core/ir/disassemble_api.h

@@ -86,15 +86,21 @@ typedef enum {
      * \p -syntax_arm.  Implicit operands are not displayed.
      */
     DR_DISASM_ARM = 0x10,
+    /**
+     * Requests RISC-V assembler syntax for disassembly. This set the same option that
+     * is controlled by the runtime option \p -syntax_riscv. Implicit oprands are not
+     * displayed.
+     */
+    DR_DISASM_RISCV = 0x20,
 } dr_disasm_flags_t;
 /* TODO i#4382: Add DR_DISASM_AARCH64. */
 
 DR_API
 /**
  * Sets the disassembly style and decoding options.
  * The default is to use DR's custom syntax, unless one of the \ref op_syntax_intel
- * "-syntax_intel", \ref op_syntax_att "-syntax_att", or \ref op_syntax_arm
- * "-syntax_arm" runtime options is specified.
+ * "-syntax_intel", \ref op_syntax_att "-syntax_att", \ref op_syntax_arm
+ * "-syntax_arm", or \ref op_syntax_riscv "-syntax_riscv" runtime options is specified.
  */
 void
 disassemble_set_syntax(dr_disasm_flags_t flags);

core/ir/disassemble_shared.c

@@ -129,6 +129,9 @@ disassemble_options_init(void)
     if (DYNAMO_OPTION(syntax_arm)) {
         flags |= DR_DISASM_ARM;
     }
+    if (DYNAMO_OPTION(syntax_riscv)) {
+        flags |= DR_DISASM_RISCV;
+    }
     /* This option is separate as it's not strictly a disasm style */
     dynamo_options.decode_strict = TEST(DR_DISASM_STRICT_INVALID, flags);
     if (DYNAMO_OPTION(decode_strict))
@@ -154,7 +157,8 @@ disassemble_set_syntax(dr_disasm_flags_t flags)
 static inline bool
 dsts_first(void)
 {
-    return TESTANY(DR_DISASM_INTEL | DR_DISASM_ARM, DYNAMO_OPTION(disasm_mask));
+    return TESTANY(DR_DISASM_INTEL | DR_DISASM_ARM | DR_DISASM_RISCV,
+                   DYNAMO_OPTION(disasm_mask));
 }
 
 static inline bool
@@ -170,7 +174,7 @@ internal_instr_disassemble(char *buf, size_t bufsz, size_t *sofar INOUT,
 static inline const char *
 immed_prefix(void)
 {
-    return (TEST(DR_DISASM_INTEL, DYNAMO_OPTION(disasm_mask))
+    return (TEST(DR_DISASM_INTEL | DR_DISASM_RISCV, DYNAMO_OPTION(disasm_mask))
                 ? ""
                 : (TEST(DR_DISASM_ARM, DYNAMO_OPTION(disasm_mask)) ? "#" : "$"));
 }
@@ -180,7 +184,8 @@ reg_disassemble(char *buf, size_t bufsz, size_t *sofar INOUT, reg_id_t reg,
                 dr_opnd_flags_t flags, const char *prefix, const char *suffix)
 {
     print_to_buffer(buf, bufsz, sofar,
-                    TESTANY(DR_DISASM_INTEL | DR_DISASM_ARM, DYNAMO_OPTION(disasm_mask))
+                    TESTANY(DR_DISASM_INTEL | DR_DISASM_ARM | DR_DISASM_RISCV,
+                            DYNAMO_OPTION(disasm_mask))
                         ? "%s%s%s%s"
                         : "%s%s%%%s%s",
                     prefix, TEST(DR_OPND_NEGATED, flags) ? "-" : "", reg_names[reg],
@@ -401,6 +406,9 @@ opnd_base_disp_disassemble(char *buf, size_t bufsz, size_t *sofar INOUT, opnd_t
         }
         if (TEST(DR_DISASM_ARM, DYNAMO_OPTION(disasm_mask)))
             print_to_buffer(buf, bufsz, sofar, "%d", disp);
+        else if (TEST(DR_DISASM_RISCV, DYNAMO_OPTION(disasm_mask)) &&
+                 TEST(opnd_get_flags(opnd), DR_OPND_IMM_PRINT_DECIMAL))
+            print_to_buffer(buf, bufsz, sofar, "%d", disp);
         else if ((unsigned)disp <= 0xff && !opnd_is_disp_force_full(opnd))
             print_to_buffer(buf, bufsz, sofar, "0x%02x", disp);
         else if ((unsigned)disp <= 0xffff IF_X86(&&opnd_is_disp_short_addr(opnd)))

core/ir/encode_shared.c

@@ -69,7 +69,7 @@ instr_encode_arch(dcontext_t *dcontext, instr_t *instr, byte *copy_pc, byte *fin
                   bool *has_instr_opnds /*OUT OPTIONAL*/
                       _IF_DEBUG(bool assert_reachable));
 
-#ifdef AARCH64
+#if defined(AARCH64) || defined(RISCV64)
 /* exported
  */
 bool

core/ir/instr_inline_api.h

@@ -343,12 +343,12 @@ opnd_create_pc(app_pc pc)
              .value.reg_and_element_size.reg)
 #    define opnd_get_reg OPND_GET_REG
 
-#    if defined(X86) || defined(RISCV64)
+#    if defined(X86)
 #        define OPND_GET_FLAGS(opnd)                                                     \
             (CLIENT_ASSERT_(                                                             \
                 opnd_is_reg(opnd) || opnd_is_base_disp(opnd) || opnd_is_immed_int(opnd), \
                 "opnd_get_flags called on non-reg non-base-disp non-immed-int opnd") 0)
-#    elif defined(AARCHXX)
+#    elif defined(AARCHXX) || defined(RISCV64)
 #        define OPND_GET_FLAGS(opnd)                                                   \
             (CLIENT_ASSERT_(                                                           \
                  opnd_is_reg(opnd) || opnd_is_base_disp(opnd) ||                       \

core/ir/opnd_api.h

@@ -1174,7 +1174,6 @@ enum {
     DR_REG_X29,     /**< The x29(t4) register. */
     DR_REG_X30,     /**< The x30(t5) register. */
     DR_REG_X31,     /**< The x31(t6) register. */
-    DR_REG_PC,      /**< The program counter. */
     /* GPR aliases */
     DR_REG_ZERO = DR_REG_X0, /**< The hard-wired zero (x0) register. */
     DR_REG_RA = DR_REG_X1,   /**< The return address (x1) register. */
@@ -1209,6 +1208,7 @@ enum {
     DR_REG_T4 = DR_REG_X29,  /**< The 5th temporary (x29) register. */
     DR_REG_T5 = DR_REG_X30,  /**< The 6th temporary (x30) register. */
     DR_REG_T6 = DR_REG_X31,  /**< The 7th temporary (x31) register. */
+    DR_REG_PC,               /**< The program counter. */
     /* Floating point registers */
     DR_REG_F0,   /**< The f0(ft0) floating-point register. */
     DR_REG_F1,   /**< The f1(ft1) floating-point register. */
@@ -1285,9 +1285,9 @@ enum {
     DR_REG_LAST_ENUM = DR_REG_FCSR,       /**< Last value of register enums. */
 
     DR_REG_START_64 = DR_REG_X0,  /**< Start of 64-bit general register enum values. */
-    DR_REG_STOP_64 = DR_REG_X31,  /**< End of 64-bit general register enum values. */
+    DR_REG_STOP_64 = DR_REG_F31,  /**< End of 64-bit general register enum values. */
     DR_REG_START_32 = DR_REG_X0,  /**< Start of 32-bit general register enum values. */
-    DR_REG_STOP_32 = DR_REG_X31,  /**< End of 32-bit general register enum values. */
+    DR_REG_STOP_32 = DR_REG_F31,  /**< End of 32-bit general register enum values. */
     DR_REG_START_GPR = DR_REG_X0, /**< Start of general register registers. */
     DR_REG_STOP_GPR = DR_REG_X31, /**< End of general register registers. */
     DR_REG_XSP = DR_REG_SP, /**< Platform-independent way to refer to stack pointer. */
@@ -1780,6 +1780,11 @@ typedef enum _dr_opnd_flags_t {
      * SVE predicate constraint
      */
     DR_OPND_IS_PREDICATE_CONSTRAINT = 0x800,
+
+    /**
+     * This is used by RISCV64 for immediates display format.
+     */
+    DR_OPND_IMM_PRINT_DECIMAL = 0x1000,
 } dr_opnd_flags_t;
 
 #ifdef DR_FAST_IR
@@ -2171,7 +2176,8 @@ DR_API
  *    needs to be specified for an absolute address; otherwise, simply
  *    use the desired short registers for base and/or index).
  *
- * (The encoding optimization flags are all false when using opnd_create_base_disp()).
+ * (The encoding optimization flags are all false when using
+ * opnd_create_base_disp()).
  */
 opnd_t
 opnd_create_base_disp_ex(reg_id_t base_reg, reg_id_t index_reg, int scale, int disp,