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i#3044 AArch64 SVE codec: Add memory tagged load/stores #6215

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merged 2 commits into from
Jul 18, 2023

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This patch adds the appropriate macros, tests and codec entries to decode and encode the following instructions:

LDG     <Xt>, [<Xn|SP>, #<simm>]
ST2G    <Xt>, [<Xn|SP>], #<simm>
ST2G    <Xt>, [<Xn|SP>, #<simm>]!
ST2G    <Xt>, [<Xn|SP>, #<simm>]
STG     <Xt>, [<Xn|SP>], #<simm>
STG     <Xt>, [<Xn|SP>, #<simm>]!
STG     <Xt>, [<Xn|SP>, #<simm>]
STZ2G   <Xt>, [<Xn|SP>], #<simm>
STZ2G   <Xt>, [<Xn|SP>, #<simm>]!
STZ2G   <Xt>, [<Xn|SP>, #<simm>]
STZG    <Xt>, [<Xn|SP>], #<simm>
STZG    <Xt>, [<Xn|SP>, #<simm>]!
STZG    <Xt>, [<Xn|SP>, #<simm>]
STGP    <Xt>, <Xt2>, [<Xn|SP>], #<simm>
STGP    <Xt>, <Xt2>, [<Xn|SP>, #<simm>]!
STGP    <Xt>, <Xt2>, [<Xn|SP>, #<simm>]

Issue #3044

This patch adds the appropriate macros, tests and codec
entries to decode and encode the following instructions:
LDG     <Xt>, [<Xn|SP>, #<simm>]
ST2G    <Xt>, [<Xn|SP>], #<simm>
ST2G    <Xt>, [<Xn|SP>, #<simm>]!
ST2G    <Xt>, [<Xn|SP>, #<simm>]
STG     <Xt>, [<Xn|SP>], #<simm>
STG     <Xt>, [<Xn|SP>, #<simm>]!
STG     <Xt>, [<Xn|SP>, #<simm>]
STZ2G   <Xt>, [<Xn|SP>], #<simm>
STZ2G   <Xt>, [<Xn|SP>, #<simm>]!
STZ2G   <Xt>, [<Xn|SP>, #<simm>]
STZG    <Xt>, [<Xn|SP>], #<simm>
STZG    <Xt>, [<Xn|SP>, #<simm>]!
STZG    <Xt>, [<Xn|SP>, #<simm>]
STGP    <Xt>, <Xt2>, [<Xn|SP>], #<simm>
STGP    <Xt>, <Xt2>, [<Xn|SP>, #<simm>]!
STGP    <Xt>, <Xt2>, [<Xn|SP>, #<simm>]

Issue #3044
Change-Id: If76ed05ce2e5191a706d5e874f2b1d77db6d5c67
@cmannett85-arm cmannett85-arm added this pull request to the merge queue Jul 18, 2023
Merged via the queue into master with commit 1498622 Jul 18, 2023
@cmannett85-arm cmannett85-arm deleted the i3044-mem-tagged-ldst branch July 18, 2023 13:22
ivankyluk pushed a commit to ivankyluk/dynamorio that referenced this pull request Jul 28, 2023
This patch adds the appropriate macros, tests and codec entries to
decode and encode the following instructions:
```
LDG     <Xt>, [<Xn|SP>, #<simm>]
ST2G    <Xt>, [<Xn|SP>], #<simm>
ST2G    <Xt>, [<Xn|SP>, #<simm>]!
ST2G    <Xt>, [<Xn|SP>, #<simm>]
STG     <Xt>, [<Xn|SP>], #<simm>
STG     <Xt>, [<Xn|SP>, #<simm>]!
STG     <Xt>, [<Xn|SP>, #<simm>]
STZ2G   <Xt>, [<Xn|SP>], #<simm>
STZ2G   <Xt>, [<Xn|SP>, #<simm>]!
STZ2G   <Xt>, [<Xn|SP>, #<simm>]
STZG    <Xt>, [<Xn|SP>], #<simm>
STZG    <Xt>, [<Xn|SP>, #<simm>]!
STZG    <Xt>, [<Xn|SP>, #<simm>]
STGP    <Xt>, <Xt2>, [<Xn|SP>], #<simm>
STGP    <Xt>, <Xt2>, [<Xn|SP>, #<simm>]!
STGP    <Xt>, <Xt2>, [<Xn|SP>, #<simm>]
```
Issue DynamoRIO#3044

Co-authored-by: Joshua Warburton <[email protected]>
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