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i#6585: Add drcachesim vector length trace marker #6603

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Feb 9, 2024
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i#6585: Add drcachesim vector length trace marker #6603

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a54610b
i#6585: Add drcachesim vector length trace marker
jackgallagher-arm Jan 26, 2024
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jackgallagher-arm Feb 1, 2024
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Move vl handling to mid-trace processing
jackgallagher-arm Feb 2, 2024
99be95a
Set vl in opcode_mix
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Check vl in invariant_checker
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Remove redundant ()
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Update documentation
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Merge branch 'master' into i6585--add-vector-length-marker
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Fix typo
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Fix name in docs
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Remove DYNAMIC from marker name
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Merge branch 'master' into i6585--add-vector-length-marker
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Merge branch 'master' into i6585--add-vector-length-marker
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7 changes: 7 additions & 0 deletions clients/drcachesim/common/trace_entry.h
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Expand Up @@ -612,6 +612,13 @@ typedef enum {
*/
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TRACE_MARKER_TYPE_CONTEXT_SWITCH_END,

/**
* The marker is used to indicate the current vector length in bytes for
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* architectures with a dynamic vector length, for example the AArch64 SVE vector
* length. This does not apply to fixed length vector architectures.
*/
TRACE_MARKER_TYPE_DYNAMIC_VECTOR_LENGTH,

// ...
// These values are reserved for future built-in marker types.
// ...
Expand Down
9 changes: 9 additions & 0 deletions clients/drcachesim/tests/allasm-scattergather-vl-view-aarch64.templatex
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@@ -0,0 +1,9 @@
.*
#if __ARM_FEATURE_SVE_BITS == 128
.*<marker: vector length 16 bytes>
#elif __ARM_FEATURE_SVE_BITS == 256
.*<marker: vector length 32 bytes>
#elif __ARM_FEATURE_SVE_BITS == 512
.*<marker: vector length 64 bytes>
#endif
.*
115 changes: 60 additions & 55 deletions clients/drcachesim/tests/allasm_scattergather_aarch64.asm
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Expand Up @@ -292,75 +292,75 @@ test_scalar_plus_scalar:


test_scalar_plus_immediate:
ld1b DEST_REG1.b, B_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 16
ld1b DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 8
ld1b DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 4
ld1b DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ldnt1b DEST_REG1.b, B_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 16
ld1sb DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 8
ld1sb DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 4
ld1sb DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ld1h DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 8
ld1h DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 4
ld1h DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ldnt1h DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 8
ld1sh DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 4
ld1sh DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ld1w DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 4
ld1w DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ldnt1w DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 4
ld1sw DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ld1d DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ldnt1d DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 2
ld1b DEST_REG1.b, B_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 16
ld1b DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 8
ld1b DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 4
ld1b DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
ldnt1b DEST_REG1.b, B_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 16
ld1sb DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 8
ld1sb DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 4
ld1sb DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
ld1h DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 8
ld1h DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 4
ld1h DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
ldnt1h DEST_REG1.h, H_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 8
ld1sh DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 4
ld1sh DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
ld1w DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 4
ld1w DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
ldnt1w DEST_REG1.s, S_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 4
ld1sw DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
ld1d DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
ldnt1d DEST_REG1.d, D_MASK_REG/z, [BUFFER_REG, #1, mul vl] // 2
// Total: 104

ld2b { DEST_REG1.b, DEST_REG2.b }, B_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 32
ld2h { DEST_REG1.h, DEST_REG2.h }, H_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 16
ld2w { DEST_REG1.s, DEST_REG2.s }, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 8
ld2d { DEST_REG1.d, DEST_REG2.d }, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 4
ld2b { DEST_REG1.b, DEST_REG2.b }, B_MASK_REG/z, [BUFFER_REG, #2, mul vl] // 32
ld2h { DEST_REG1.h, DEST_REG2.h }, H_MASK_REG/z, [BUFFER_REG, #2, mul vl] // 16
ld2w { DEST_REG1.s, DEST_REG2.s }, S_MASK_REG/z, [BUFFER_REG, #2, mul vl] // 8
ld2d { DEST_REG1.d, DEST_REG2.d }, D_MASK_REG/z, [BUFFER_REG, #2, mul vl] // 4
// Total: 60

ld3b { DEST_REG1.b, DEST_REG2.b, DEST_REG3.b }, B_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 48
ld3h { DEST_REG1.h, DEST_REG2.h, DEST_REG3.h }, H_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 24
ld3w { DEST_REG1.s, DEST_REG2.s, DEST_REG3.s }, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 12
ld3d { DEST_REG1.d, DEST_REG2.d, DEST_REG3.d }, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 6
ld3b { DEST_REG1.b, DEST_REG2.b, DEST_REG3.b }, B_MASK_REG/z, [BUFFER_REG, #3, mul vl] // 48
ld3h { DEST_REG1.h, DEST_REG2.h, DEST_REG3.h }, H_MASK_REG/z, [BUFFER_REG, #3, mul vl] // 24
ld3w { DEST_REG1.s, DEST_REG2.s, DEST_REG3.s }, S_MASK_REG/z, [BUFFER_REG, #3, mul vl] // 12
ld3d { DEST_REG1.d, DEST_REG2.d, DEST_REG3.d }, D_MASK_REG/z, [BUFFER_REG, #3, mul vl] // 6
// Total: 90

ld4b { DEST_REG1.b, DEST_REG2.b, DEST_REG3.b, DEST_REG4.b }, B_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 64
ld4h { DEST_REG1.h, DEST_REG2.h, DEST_REG3.h, DEST_REG4.h }, H_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 32
ld4w { DEST_REG1.s, DEST_REG2.s, DEST_REG3.s, DEST_REG4.s }, S_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 16
ld4d { DEST_REG1.d, DEST_REG2.d, DEST_REG3.d, DEST_REG4.d }, D_MASK_REG/z, [BUFFER_REG, #0, mul vl] // 8
ld4b { DEST_REG1.b, DEST_REG2.b, DEST_REG3.b, DEST_REG4.b }, B_MASK_REG/z, [BUFFER_REG, #4, mul vl] // 64
ld4h { DEST_REG1.h, DEST_REG2.h, DEST_REG3.h, DEST_REG4.h }, H_MASK_REG/z, [BUFFER_REG, #4, mul vl] // 32
ld4w { DEST_REG1.s, DEST_REG2.s, DEST_REG3.s, DEST_REG4.s }, S_MASK_REG/z, [BUFFER_REG, #4, mul vl] // 16
ld4d { DEST_REG1.d, DEST_REG2.d, DEST_REG3.d, DEST_REG4.d }, D_MASK_REG/z, [BUFFER_REG, #4, mul vl] // 8
// Total: 120
// Total loads: 104 + 60 + 90 + 120 = 374

st1b SRC_REG1.b, B_MASK_REG, [BUFFER_REG, #0, mul vl] // 16
st1b SRC_REG1.h, H_MASK_REG, [BUFFER_REG, #0, mul vl] // 8
st1b SRC_REG1.s, S_MASK_REG, [BUFFER_REG, #0, mul vl] // 4
st1b SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #0, mul vl] // 2
st1h SRC_REG1.h, H_MASK_REG, [BUFFER_REG, #0, mul vl] // 8
st1h SRC_REG1.s, S_MASK_REG, [BUFFER_REG, #0, mul vl] // 4
st1h SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #0, mul vl] // 2
st1w SRC_REG1.s, S_MASK_REG, [BUFFER_REG, #0, mul vl] // 4
st1w SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #0, mul vl] // 2
st1d SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #0, mul vl] // 2
st1b SRC_REG1.b, B_MASK_REG, [BUFFER_REG, #1, mul vl] // 16
st1b SRC_REG1.h, H_MASK_REG, [BUFFER_REG, #1, mul vl] // 8
st1b SRC_REG1.s, S_MASK_REG, [BUFFER_REG, #1, mul vl] // 4
st1b SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #1, mul vl] // 2
st1h SRC_REG1.h, H_MASK_REG, [BUFFER_REG, #1, mul vl] // 8
st1h SRC_REG1.s, S_MASK_REG, [BUFFER_REG, #1, mul vl] // 4
st1h SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #1, mul vl] // 2
st1w SRC_REG1.s, S_MASK_REG, [BUFFER_REG, #1, mul vl] // 4
st1w SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #1, mul vl] // 2
st1d SRC_REG1.d, D_MASK_REG, [BUFFER_REG, #1, mul vl] // 2
// Total: 52

st2b { SRC_REG1.b, SRC_REG2.b }, B_MASK_REG, [BUFFER_REG, #0, mul vl] // 32
st2h { SRC_REG1.h, SRC_REG2.h }, H_MASK_REG, [BUFFER_REG, #0, mul vl] // 16
st2w { SRC_REG1.s, SRC_REG2.s }, S_MASK_REG, [BUFFER_REG, #0, mul vl] // 8
st2d { SRC_REG1.d, SRC_REG2.d }, D_MASK_REG, [BUFFER_REG, #0, mul vl] // 4
st2b { SRC_REG1.b, SRC_REG2.b }, B_MASK_REG, [BUFFER_REG, #2, mul vl] // 32
st2h { SRC_REG1.h, SRC_REG2.h }, H_MASK_REG, [BUFFER_REG, #2, mul vl] // 16
st2w { SRC_REG1.s, SRC_REG2.s }, S_MASK_REG, [BUFFER_REG, #2, mul vl] // 8
st2d { SRC_REG1.d, SRC_REG2.d }, D_MASK_REG, [BUFFER_REG, #2, mul vl] // 4
// Total: 60

st3b { SRC_REG1.b, SRC_REG2.b, SRC_REG3.b }, B_MASK_REG, [BUFFER_REG, #0, mul vl] // 48
st3h { SRC_REG1.h, SRC_REG2.h, SRC_REG3.h }, H_MASK_REG, [BUFFER_REG, #0, mul vl] // 24
st3w { SRC_REG1.s, SRC_REG2.s, SRC_REG3.s }, S_MASK_REG, [BUFFER_REG, #0, mul vl] // 12
st3d { SRC_REG1.d, SRC_REG2.d, SRC_REG3.d }, D_MASK_REG, [BUFFER_REG, #0, mul vl] // 6
st3b { SRC_REG1.b, SRC_REG2.b, SRC_REG3.b }, B_MASK_REG, [BUFFER_REG, #3, mul vl] // 48
st3h { SRC_REG1.h, SRC_REG2.h, SRC_REG3.h }, H_MASK_REG, [BUFFER_REG, #3, mul vl] // 24
st3w { SRC_REG1.s, SRC_REG2.s, SRC_REG3.s }, S_MASK_REG, [BUFFER_REG, #3, mul vl] // 12
st3d { SRC_REG1.d, SRC_REG2.d, SRC_REG3.d }, D_MASK_REG, [BUFFER_REG, #3, mul vl] // 6
// Total: 90

st4b { SRC_REG1.b, SRC_REG2.b, SRC_REG3.b, SRC_REG4.b }, B_MASK_REG, [BUFFER_REG, #0, mul vl] // 64
st4h { SRC_REG1.h, SRC_REG2.h, SRC_REG3.h, SRC_REG4.h }, H_MASK_REG, [BUFFER_REG, #0, mul vl] // 32
st4w { SRC_REG1.s, SRC_REG2.s, SRC_REG3.s, SRC_REG4.s }, S_MASK_REG, [BUFFER_REG, #0, mul vl] // 16
st4d { SRC_REG1.d, SRC_REG2.d, SRC_REG3.d, SRC_REG4.d }, D_MASK_REG, [BUFFER_REG, #0, mul vl] // 8
st4b { SRC_REG1.b, SRC_REG2.b, SRC_REG3.b, SRC_REG4.b }, B_MASK_REG, [BUFFER_REG, #4, mul vl] // 64
st4h { SRC_REG1.h, SRC_REG2.h, SRC_REG3.h, SRC_REG4.h }, H_MASK_REG, [BUFFER_REG, #4, mul vl] // 32
st4w { SRC_REG1.s, SRC_REG2.s, SRC_REG3.s, SRC_REG4.s }, S_MASK_REG, [BUFFER_REG, #4, mul vl] // 16
st4d { SRC_REG1.d, SRC_REG2.d, SRC_REG3.d, SRC_REG4.d }, D_MASK_REG, [BUFFER_REG, #4, mul vl] // 8
// Total: 120
// Total stores: 52 + 60 + 90 + 120 = 322

Expand Down Expand Up @@ -557,4 +557,9 @@ helloworld:
.ascii "Hello, world!\n"

buffer:
.zero 1024 // Maximum size of an SVE Z register * 4.
.zero 2048 // Maximum size of an SVE Z register * 8.
// This gives us enough space to use an offset of
// #1, mul vl for scalar+immediate/vector+immediate
// instructions which lets us check the VL scaling of
// offsets in the IR in
// tool.drcacheoff.allasm-scattergather-vl-view
15 changes: 15 additions & 0 deletions clients/drcachesim/tests/offline-allasm-scattergather-vl-view-aarch64.templatex
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Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
.*
#if __ARM_FEATURE_SVE_BITS == 128
.*<marker: vector length 16 bytes>
.*a401a03c ld1b \+0x10\(%x1\)\[1byte\] %p0/z -> %z28\.b
.*e5d1ec3c st3d %z28\.d %z29\.d %z30\.d %p3 -> \+0x30\(%x1\)\[8byte\]
#elif __ARM_FEATURE_SVE_BITS == 256
.*<marker: vector length 32 bytes>
.*a401a03c ld1b \+0x20\(%x1\)\[1byte\] %p0/z -> %z28.b
.*e5d1ec3c st3d %z28\.d %z29\.d %z30\.d %p3 -> \+0x60\(%x1\)\[8byte\]
#elif __ARM_FEATURE_SVE_BITS == 512
.*<marker: vector length 64 bytes>
.*a401a03c ld1b \+0x40\(%x1\)\[1byte\] %p0/z -> %z28.b
.*e5d1ec3c st3d %z28\.d %z29\.d %z30\.d %p3 -> \+0xc0\(%x1\)\[8byte\]
#endif
.*
9 changes: 9 additions & 0 deletions clients/drcachesim/tests/offline-view.templatex
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Expand Up @@ -5,11 +5,20 @@ Output format:
1 0: +[0-9]+ <marker: version [0-9]>
2 0: +[0-9]+ <marker: filetype 0x[0-9a-f]*>
3 0: +[0-9]+ <marker: cache line size [0-9]*>
#ifdef __ARM_FEATURE_SVE
4 0: +[0-9]+ <marker: vector length [0-9]* bytes>
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5 0: +[0-9]+ <marker: chunk instruction count [0-9]*>
6 0: +[0-9]+ <marker: page size [0-9]*>
7 0: +[0-9]+ <marker: timestamp [0-9]*>
8 0: +[0-9]+ <marker: tid [0-9]* on core [0-9]*>
9 1: +[0-9]+ ifetch .*
#else
4 0: +[0-9]+ <marker: chunk instruction count [0-9]*>
5 0: +[0-9]+ <marker: page size [0-9]*>
6 0: +[0-9]+ <marker: timestamp [0-9]*>
7 0: +[0-9]+ <marker: tid [0-9]* on core [0-9]*>
8 1: +[0-9]+ ifetch .*
#endif
.*
View tool results:
*[0-9]* : total instructions
59 changes: 33 additions & 26 deletions clients/drcachesim/tests/view_test.cpp
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Expand Up @@ -305,6 +305,7 @@ run_limit_tests(void *drcontext)
gen_marker(t1, TRACE_MARKER_TYPE_VERSION, 3),
gen_marker(t1, TRACE_MARKER_TYPE_FILETYPE, 0),
gen_marker(t1, TRACE_MARKER_TYPE_CACHE_LINE_SIZE, 64),
gen_marker(t1, TRACE_MARKER_TYPE_DYNAMIC_VECTOR_LENGTH, 32),
gen_marker(t1, TRACE_MARKER_TYPE_TIMESTAMP, 1001),
gen_marker(t1, TRACE_MARKER_TYPE_CPU_ID, 2),
gen_instr(t1, offs_nop1),
Expand Down Expand Up @@ -463,6 +464,7 @@ run_single_thread_chunk_test(void *drcontext)
{ TRACE_TYPE_THREAD, 0, { t1 } },
{ TRACE_TYPE_PID, 0, { t1 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CACHE_LINE_SIZE, { 64 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_DYNAMIC_VECTOR_LENGTH, { 16 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CHUNK_INSTR_COUNT, { 2 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_TIMESTAMP, { 1002 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CPU_ID, { 2 } },
Expand All @@ -478,13 +480,14 @@ run_single_thread_chunk_test(void *drcontext)
const char *expect = R"DELIM( 1 0: 3 <marker: version 3>
2 0: 3 <marker: filetype 0x0>
3 0: 3 <marker: cache line size 64>
4 0: 3 <marker: chunk instruction count 2>
5 0: 3 <marker: timestamp 1002>
6 0: 3 <marker: tid 3 on core 2>
7 1: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
8 2: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
9 2: 3 <marker: chunk footer #0>
10 3: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
4 0: 3 <marker: vector length 16 bytes>
5 0: 3 <marker: chunk instruction count 2>
6 0: 3 <marker: timestamp 1002>
7 0: 3 <marker: tid 3 on core 2>
8 1: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
9 2: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
10 2: 3 <marker: chunk footer #0>
11 3: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
)DELIM";
instrlist_t *ilist_unused = nullptr;
view_nomod_test_t view(drcontext, *ilist_unused, 0, 0);
Expand Down Expand Up @@ -515,6 +518,7 @@ run_serial_chunk_test(void *drcontext)
{ TRACE_TYPE_THREAD, 0, { t1 } },
{ TRACE_TYPE_PID, 0, { t1 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CACHE_LINE_SIZE, { 64 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_DYNAMIC_VECTOR_LENGTH, { 16 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CHUNK_INSTR_COUNT, { 20 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_TIMESTAMP, { 1001 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CPU_ID, { 2 } },
Expand All @@ -531,6 +535,7 @@ run_serial_chunk_test(void *drcontext)
{ TRACE_TYPE_THREAD, 0, { t2 } },
{ TRACE_TYPE_PID, 0, { t2 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CACHE_LINE_SIZE, { 64 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_DYNAMIC_VECTOR_LENGTH, { 16 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CHUNK_INSTR_COUNT, { 2 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_TIMESTAMP, { 1002 } },
{ TRACE_TYPE_MARKER, TRACE_MARKER_TYPE_CPU_ID, { 2 } },
Expand All @@ -545,28 +550,30 @@ run_serial_chunk_test(void *drcontext)
R"DELIM( 1 0: 3 <marker: version 3>
2 0: 3 <marker: filetype 0x0>
3 0: 3 <marker: cache line size 64>
4 0: 3 <marker: chunk instruction count 20>
5 0: 3 <marker: timestamp 1001>
6 0: 3 <marker: tid 3 on core 2>
7 1: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
8 2: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
4 0: 3 <marker: vector length 16 bytes>
5 0: 3 <marker: chunk instruction count 20>
6 0: 3 <marker: timestamp 1001>
7 0: 3 <marker: tid 3 on core 2>
8 1: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
9 2: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
------------------------------------------------------------
9 2: 7 <marker: version 3>
10 2: 7 <marker: filetype 0x0>
11 2: 7 <marker: cache line size 64>
12 2: 7 <marker: chunk instruction count 2>
13 2: 7 <marker: timestamp 1002>
14 2: 7 <marker: tid 7 on core 2>
15 3: 7 ifetch 4 byte(s) @ 0x0000002a non-branch
16 4: 7 ifetch 4 byte(s) @ 0x0000002a non-branch
10 2: 7 <marker: version 3>
11 2: 7 <marker: filetype 0x0>
12 2: 7 <marker: cache line size 64>
13 2: 7 <marker: vector length 16 bytes>
14 2: 7 <marker: chunk instruction count 2>
15 2: 7 <marker: timestamp 1002>
16 2: 7 <marker: tid 7 on core 2>
17 3: 7 ifetch 4 byte(s) @ 0x0000002a non-branch
18 4: 7 ifetch 4 byte(s) @ 0x0000002a non-branch
------------------------------------------------------------
17 4: 3 <marker: timestamp 1003>
18 4: 3 <marker: tid 3 on core 3>
19 5: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
19 4: 3 <marker: timestamp 1003>
20 4: 3 <marker: tid 3 on core 3>
21 5: 3 ifetch 4 byte(s) @ 0x0000002a non-branch
------------------------------------------------------------
20 5: 7 <marker: timestamp 1004>
21 5: 7 <marker: tid 7 on core 3>
22 6: 7 ifetch 4 byte(s) @ 0x0000002a non-branch
22 5: 7 <marker: timestamp 1004>
23 5: 7 <marker: tid 7 on core 3>
24 6: 7 ifetch 4 byte(s) @ 0x0000002a non-branch
)DELIM";
instrlist_t *ilist_unused = nullptr;
view_nomod_test_t view(drcontext, *ilist_unused, 0, 0);
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