Merge pull request #201 from jedwards4b/cleanup_testlist

Description of changes

Remove test systems bluewaters, hobart and edison from testlists
Specific notes

Contributors other than yourself, if any:

Fixes: [Github issue #s] And brief description of each issue.

User interface changes?: [ No/Yes ]
[ If yes, describe what changed, and steps taken to ensure backward compatibility ]

Testing performed (automated tests and/or manual tests):

cime_config/testlist_allactive.xml

@@ -1,21 +1,5 @@
 <?xml version="1.0"?>
 <testlist version="2.0">
-  <test name="ERI" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="bluewaters" compiler="pgi" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 01:00 </option>
-    </options>
-  </test>
-  <test name="ERI" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="edison" compiler="intel" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 01:00 </option>
-    </options>
-  </test>
   <test name="ERI" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
     <machines>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
@@ -40,22 +24,6 @@
       <option name="wallclock"> 00:30:00 </option>
     </options>
   </test>
-  <test name="ERR" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="edison" compiler="intel" category="prealpha"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 00:30 </option>
-    </options>
-  </test>
-  <test name="MCC" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="edison" compiler="intel" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 02:00 </option>
-    </options>
-  </test>
   <test name="MCC" grid="f19_g17" compset="B1850" testmods="allactive/defaultiomi">
     <machines>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
@@ -80,26 +48,8 @@
       <option name="wallclock"> 06:00:00 </option>
     </options>
   </test>
-  <test name="IRT" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="bluewaters" compiler="pgi" category="prebeta"/>
-    </machines>
-    <options>
-       <option name="wallclock"> 00:30 </option>
-    </options>
-  </test>
-  <test name="IRT" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="bluewaters" compiler="pgi" category="prealpha"/>
-      <machine name="edison" compiler="cray" category="prealpha"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 00:40 </option>
-    </options>
-  </test>
   <test name="IRT_Ld7" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
     <machines>
-      <machine name="bluewaters" compiler="pgi" category="prebeta"/>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
     </machines>
     <options>
@@ -108,7 +58,6 @@
   </test>
   <test name="IRT_Ld7_Vmct" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
     <machines>
-      <machine name="bluewaters" compiler="pgi" category="prebeta"/>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
     </machines>
     <options>
@@ -160,33 +109,14 @@
   </test>
   <test name="ERS_Ld7" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
     <machines>
-      <machine name="bluewaters" compiler="pgi"   category="prebeta"/>
       <machine name="cheyenne"   compiler="intel" category="prealpha"/>
-      <machine name="hobart"     compiler="pgi"   category="prealpha"/>
     </machines>
     <options>
       <option name="wallclock"> 00:30:00 </option>
     </options>
   </test>
-  <test name="ERS_Ld7" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
-    <machines>
-      <machine name="bluewaters" compiler="pgi" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 00:30 </option>
-    </options>
-  </test>
-  <test name="ERS_Ld9" grid="ne120_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="edison" compiler="intel" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 00:30 </option>
-    </options>
-  </test>
   <test name="IRT_C3_Ld7" grid="f19_g17" compset="BHIST" testmods="allactive/defaultio">
     <machines>
-      <machine name="edison" compiler="intel" category="prebeta"/>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
       <machine name="cheyenne" compiler="gnu" category="prebeta"/>
     </machines>
@@ -223,7 +153,6 @@
   </test>
   <test name="PFS" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
     <machines>
-      <machine name="bluewaters" compiler="pgi" category="prebeta"/>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
       <machine name="cheyenne" compiler="intel" category="prebeta"/>
     </machines>
@@ -244,23 +173,6 @@
       <machine name="cheyenne" compiler="intel" category="aux_perf"/>
     </machines>
   </test>
-
-  <test name="SMS_D" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
-    <machines>
-      <machine name="edison" compiler="intel" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 00:30 </option>
-    </options>
-  </test>
-  <test name="SMS_D" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
-    <machines>
-      <machine name="edison" compiler="intel" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 00:30 </option>
-    </options>
-  </test>
   <test name="SMS_Ld5" grid="f19_g17" compset="B1850G" testmods="allactive/cism/test_coupling">
     <machines>
       <machine name="cheyenne" compiler="intel" category="prealpha"/>
@@ -277,14 +189,6 @@
       <option name="wallclock"> 00:30:00 </option>
     </options>
   </test>
-  <test name="SMS_Ld1" grid="f19_g17" compset="B1850G" testmods="allactive/cism/test_coupling">
-    <machines>
-      <machine name="hobart" compiler="nag" category="prebeta"/>
-    </machines>
-    <options>
-      <option name="wallclock"> 00:45 </option>
-    </options>
-  </test>
   <test name="SMS_Ld5" grid="f09_g17_gl4" compset="J1850G" testmods="allactive/cism/test_coupling">
     <machines>
       <machine name="cheyenne" compiler="gnu" category="prebeta"/>