In order to address the ever increasing demands of IoT, we advocate a new architectural blueprint for the design of composable and predictable multi-processor wireless sensing platforms.
BOLT is an ultra-low power processor interconnect that decouples arbitrary application and communication processors with respect to time, power and clock domains. BOLT supports asynchronous message passing with predictable timing characteristics, and therefore making it possible for the system designer to construct highly-customized platforms that are easier to design, implement, debug, and maintain.
In this repository, we provide an implementation of the BOLT processor interconnect for the 16-bit TI MSP430FR5969 microcontroller.
If you want to learn more about BOLT, please have a look at our SenSys'15 paper.
The code was developed for the MSP430FR5969 microcontroller and can be compiled with the TI Code Composer Studio. To customize BOLT, edit the parameters in the config.h file. Parameters that can be changed include the maximum message size, the number of elements in each of the two FIFO queues and whether or not the queue should be cleared after a reset. If you don't need to tune specific parameters, there are also a few precompiled BOLT binaries in the designated folder.
The BOLT code is released under 3-clause BSD license. For more details please refer the the LICENSE file.
BOLT was developed at the Computer Engineering Group at ETH Zurich. The following people contributed to the design and implementation: Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Jan Beutel, Federico Ferrari and Lothar Thiele.