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Separate fabric and tile configuration #154

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mole99
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@mole99 mole99 commented Feb 17, 2024

This PR separates the fabric and tile configuration. This has several benefits:

  • It's cleaner:
    The fabric config only describes the fabric and the Tile/ folder contains all information about tiles
    The git history for tile changes / fabric changes is separate
  • It is easier easier to swap whole "tile libraries", just point to different tiles in fabric.csv
  • Code is a bit more separated

I carefully tried to not break anything and tested this PR with both the Verilog and VHDL writers: load_fabric is successful for both of them. For Verilog all subsequent commands work as expected, for VHDL run_FABulous_fabric throws an error that is unrelated to this PR. See #153.

Fixes #149.

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We should keep the backward compatibility with the single CSV format.

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That I hadn't thought of that! Should now support the old fabric configuration format. I had to change parseTiles and parseSupertiles to return a list of objects.

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Rather than deprecation, we can introduce a new keyword, for example, TILE_PATH, to indicate a path is provided. Will also need to update the Doc to let people know this is available.

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The keywords that are used are Tile and Supertile to read the tile/supertile configuration from a path. Should I rename them?

I would keep the deprecation notice. It's not much work to move an existing fabric to the new format and the FABulous template uses the new format as well. Supporting both options is more work to maintain and I think it makes generally more sense when the configurations are split this way.

I would update the docs with the new way of describing tiles, if that's okay?

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Yes, this makes sense.

Let's keep the Tile and Supertile keywords since the TILE keyword will only happen in the "tile.csv".

Update the Doc with the new tile description method and mark deprecation for the current method. When the "2.0" release is in place, we can entirely remove the current way.

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I have now updated the docs to refer to the new method of tile description.

What I noticed: The example fabric uses the CPU_IO tile which is currently not available for Verilog and misses configurations in VHDL. I think it would be nice to have this available, should I open an issue regarding the missing files?

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Yes, open an issue about it. Someone is currently working on the automatic generation of the tile functionality. This should help with the situation.

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Done! I think this PR should be ready then.

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@KelvinChung2000
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I think you will have other significant changes as well. We will need to maintain the current file structure for a tutorial shortly. I have started a new branch called FABulous2.0-development; let's have file structure changes happen there, and when it is all ready, we can put everything into master.

@mole99 mole99 changed the base branch from master to FABulous2.0-development February 22, 2024 14:29
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mole99 commented Feb 22, 2024

Sounds good! I have changed the base branch to FABulous2.0-development.

@KelvinChung2000 KelvinChung2000 merged commit bf7f1cf into FPGA-Research-Manchester:FABulous2.0-development Feb 22, 2024
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@mole99 mole99 mentioned this pull request Feb 26, 2024
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Separate Fabric and Tile description
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