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4.9-1.0.x-imx merge latest changes from rel_imx_4.9.x_1.0.0_ga #19
4.9-1.0.x-imx merge latest changes from rel_imx_4.9.x_1.0.0_ga #19
Commits on Oct 11, 2017
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MLK-16564-01 gpio: imx-rpmsg: add rpmsg virtual gpio driver
Add rpmsg virtual gpio driver support. i.MX7ULP GPIO PTA and PTB resource are managed by M4 core, setup one simple protocol with M4 core based on RPMSG virtual IO to let A core access such GPIOs that is what the driver do. Reviewed-by: Richard Zhu <[email protected]> Reviewed-by: Robin Gong <[email protected]> Signed-off-by: Fugang Duan <[email protected]>
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MLK-16564-02 dts: imx7ulp-evk: add rpmsg gpio PTA and PTB support
Add rpmsg gpio PTA and PTB support. Since currently M4 image support dynamical channel allocation, and reserve below memory for kernel service and app channel: * --0x9FF00000~0x9FF0FFFF: pmic,pm,audio,keys,gpio * --0x9FF10000~0x9FF1FFFF: pingpong,virtual tty Change the rpmsg instances of A core part to sync with M core. Test M4 image built from Wayne Feng, M4 image commit ID: b1321d4aca82 Reviewed-by: Richard Zhu <[email protected]> Reviewed-by: Robin Gong <[email protected]> Signed-off-by: Fugang Duan <[email protected]>
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MLK-16564-03 ARM: imx_v7_defconfig: enable rpmsg gpio driver
Enable CONFIG_GPIO_IMX_RPMSG to support rpmsg gpio driver in default. Reviewed-by: Richard Zhu <[email protected]> Reviewed-by: Robin Gong <[email protected]> Signed-off-by: Fugang Duan <[email protected]>
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Commits on Oct 19, 2017
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MLK-16576 usb: phy: mxs: set hold_ring_off for USB2 PLL power up
USB2 PLL use ring VCO, when the PLL power up, the ring VCO’s supply also ramp up. There is a possibility that the ring VCO start oscillation at multi nodes in this phase, especially for VCO which has many stages, then the multiwave will kept until PLL power down. Hold_ring_off(bit11) can force the VCO in one determined state when VCO supply start ramp up, to avoid this multiwave issue. Per IC design's suggestion it's better this bit can be off from 25us after pll power up to 25us before USB TX/RX. Acked-by: Peter Chen <[email protected]> Signed-off-by: Li Jun <[email protected]> (cherry picked from commit a094377f04c9ed2c8e702ee7bfab843caa03eb96)
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Commits on Nov 20, 2017
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MLK-16266-01 ARM: imx: improve the soc revision calculation flow
On our i.MX6 SOC, the DIGPROG register is used for represent the SOC ID and silicon revision. The revision has two part: MAJOR and MINOR. each is represented in 8 bits in the register. bits [15:8]: reflect the MAJOR part of the revision; bits [7:0]: reflect the MINOR part of the revision; In our linux kernel, the soc revision is represented in 8 bits. MAJOR part and MINOR each occupy 4 bits. previous method does NOT take care about the MAJOR part in DIGPROG register. So reformat the revision read from the HW to compatible the revision format used in kernel. Signed-off-by: Bai Ping <[email protected]> (cherry picked from commit cf6fa14)
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MLK-16266-02 ARM: imx: Enhance the code to support new TO for imx6qp
Previous code don't take care about the i.MX6QP revision update of new TO. So improve the code to include future TO support for i.MX6QP. Signed-off-by: Bai Ping <[email protected]> (cherry picked from commit 513e1c9)
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