clean up files, fix doc generate

.github/workflows/ci.yml

@@ -62,7 +62,7 @@ jobs:
       - name: init mem and no ext mem
         run: make fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=1 USE_EXTMEM=0
       - name: no init mem and ext mem
-        run: make -C ../iob_soc_V* fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=0 USE_EXTMEM=1
+        run: make fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=0 USE_EXTMEM=1
 
 
   aes-ku040:
@@ -78,7 +78,7 @@ jobs:
       - name: init mem and no ext mem
         run: make fpga-run BOARD=AES-KU040-DB-G INIT_MEM=1 USE_EXTMEM=0
       - name: no init mem and ext mem
-        run: make -C ../iob_soc_V* fpga-run BOARD=AES-KU040-DB-G INIT_MEM=0 USE_EXTMEM=1
+        run: make fpga-run BOARD=AES-KU040-DB-G INIT_MEM=0 USE_EXTMEM=1
 
   doc:
     runs-on: self-hosted

document/doc_build.mk

@@ -14,13 +14,3 @@ INT_FAMILY ?=CYCLONEV-GT-DK
 #results for xilinx fpga
 XIL_FAMILY ?=AES-KU040-DB-G
 
-#tests
-TEST_LIST+=test1
-test1: pb.pdf
-	cat pb.aux >> test.log
-
-TEST_LIST+=test2
-test2: presentation.pdf
-	cat presentation.aux >> test.log
-
-.PHONY: $(TEST_LIST)

document/tsrc/presentation.tex

@@ -32,7 +32,7 @@
 \title[IOb-SoC Presentation]{IOb-SoC}
 \subtitle{Tutorial: Create a RISC-V-based System-on-Chip}
 \institute[IObundle Lda.]{IObundle Lda.}
-\titlegraphic{\includegraphics[height=2.5cm]{\TEX/figures/Logo.png}}
+\titlegraphic{\includegraphics[height=2.5cm]{figures/Logo.png}}
 %\author[José T. de Sousa]{Jos\'e T. de Sousa}
 %\institute[IObundle Lda]{IObundle Lda}
 \date{\today}
@@ -52,7 +52,7 @@
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\logo{\includegraphics[scale=0.2]{\TEX/figures/Logo.png}~%
+\logo{\includegraphics[scale=0.2]{figures/Logo.png}~%
 }
 %%%%%%%%%%%%%%%%%%%%%%%%%%
 

software/sw_build.mk

@@ -79,11 +79,3 @@ EMUL_SRC+=src/iob_str.c
 # PERIPHERAL SOURCES
 EMUL_SRC+=$(wildcard src/iob-*.c)
 
-EMUL_TEST_LIST+=pcemul_test1
-pcemul_test1:
-	make run_emul TEST_LOG="> test.log"
-
-
-CLEAN_LIST+=clean1
-clean1:
-	@rm -rf iob_soc_conf.h