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fix(SWREG): <SWREG>_ADDR as macro address; remove unused <SWREG>_rvalikd_rd signal #619

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merged 2 commits into from
Nov 3, 2023
Merged

fix(SWREG): <SWREG>_ADDR as macro address; remove unused <SWREG>_rvalikd_rd signal #619

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2115443
fix(sw): use SWREG_ADDR as macro address
P-Miranda Nov 3, 2023
aaea540
fix(hw): remove unused SWREG_rvalid_rd signal
P-Miranda Nov 3, 2023
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18 changes: 9 additions & 9 deletions hardware/simulation/src/iob_soc_tb.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -69,13 +69,13 @@ void uartread(unsigned int cpu_address, char *read_reg) {

void inituart() {
// pulse reset uart
uartwrite(IOB_UART_SOFTRESET, 1, IOB_UART_SOFTRESET_W / 8);
uartwrite(IOB_UART_SOFTRESET, 0, IOB_UART_SOFTRESET_W / 8);
uartwrite(IOB_UART_SOFTRESET_ADDR, 1, IOB_UART_SOFTRESET_W / 8);
uartwrite(IOB_UART_SOFTRESET_ADDR, 0, IOB_UART_SOFTRESET_W / 8);
// config uart div factor
uartwrite(IOB_UART_DIV, int(FREQ / BAUD), IOB_UART_DIV_W / 8);
uartwrite(IOB_UART_DIV_ADDR, int(FREQ / BAUD), IOB_UART_DIV_W / 8);
// enable uart for receiving
uartwrite(IOB_UART_RXEN, 1, IOB_UART_RXEN_W / 8);
uartwrite(IOB_UART_TXEN, 1, IOB_UART_TXEN_W / 8);
uartwrite(IOB_UART_RXEN_ADDR, 1, IOB_UART_RXEN_W / 8);
uartwrite(IOB_UART_TXEN_ADDR, 1, IOB_UART_TXEN_W / 8);
}

int main(int argc, char **argv, char **env) {
Expand Down Expand Up @@ -123,15 +123,15 @@ int main(int argc, char **argv, char **env) {
break;
}
while (!rxread_reg && !txread_reg) {
uartread(IOB_UART_RXREADY, &rxread_reg);
uartread(IOB_UART_TXREADY, &txread_reg);
uartread(IOB_UART_RXREADY_ADDR, &rxread_reg);
uartread(IOB_UART_TXREADY_ADDR, &txread_reg);
}
if (rxread_reg) {
if ((soc2cnsl_fd = fopen("./soc2cnsl", "rb")) != NULL) {
able2read = fread(&cpu_char, sizeof(char), 1, soc2cnsl_fd);
if (able2read == 0) {
fclose(soc2cnsl_fd);
uartread(IOB_UART_RXDATA, &cpu_char);
uartread(IOB_UART_RXDATA_ADDR, &cpu_char);
soc2cnsl_fd = fopen("./soc2cnsl", "wb");
fwrite(&cpu_char, sizeof(char), 1, soc2cnsl_fd);
rxread_reg = 0;
Expand All @@ -145,7 +145,7 @@ int main(int argc, char **argv, char **env) {
}
able2write = fread(&cpu_char, sizeof(char), 1, cnsl2soc_fd);
if (able2write > 0) {
uartwrite(IOB_UART_TXDATA, cpu_char, IOB_UART_TXDATA_W / 8);
uartwrite(IOB_UART_TXDATA_ADDR, cpu_char, IOB_UART_TXDATA_W / 8);
fclose(cnsl2soc_fd);
cnsl2soc_fd = fopen("./cnsl2soc", "w");
}
Expand Down
2 changes: 1 addition & 1 deletion software/src/iob_soc_boot.c
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Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ int main() {
uart_txwait();

#ifdef USE_EXTMEM
while (!cache_wtb_empty())
while (!IOB_CACHE_GET_WTB_EMPTY())
;
#endif
}
2 changes: 1 addition & 1 deletion submodules/CACHE
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Submodule CACHE updated 2 files
+1 −24 software/src/iob-cache.c
+1 −15 software/src/iob-cache.h
15 changes: 8 additions & 7 deletions submodules/LIB/scripts/mkregs.py
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Original file line number Diff line number Diff line change
Expand Up @@ -529,12 +529,13 @@ def write_hwcode(self, table, out_dir, top):

# iob_rvalid_nxt output
f_gen.write("//iob_rvalid_nxt output\n")
f_gen.write("assign iob_rvalid_nxt_o = iob_avalid_i & iob_ready_o & (!iob_wstrb_i);\n\n")

f_gen.write(
"assign iob_rvalid_nxt_o = iob_avalid_i & iob_ready_o & (!iob_wstrb_i);\n\n"
)

# iob_rdata_o output
f_gen.write("assign iob_rdata_o = rdata_int;\n\n")



f_gen.write("endmodule\n")
f_gen.close()
f_inst.close()
Expand Down Expand Up @@ -630,7 +631,7 @@ def write_swheader(self, table, out_dir, top):
for row in table:
name = row["name"]
if "W" in row["type"] or "R" in row["type"]:
fswhdr.write(f"#define {core_prefix}{name} {row['addr']}\n")
fswhdr.write(f"#define {core_prefix}{name}_ADDR {row['addr']}\n")

fswhdr.write("\n//Data widths (bit)\n")
for row in table:
Expand Down Expand Up @@ -706,7 +707,7 @@ def write_swcode(self, table, out_dir, top):
f"void {core_prefix}SET_{name}({sw_type} value{addr_arg}) {{\n"
)
fsw.write(
f" (*( (volatile {sw_type} *) ( (base) + ({core_prefix}{name}){addr_shift}) ) = (value));\n"
f" (*( (volatile {sw_type} *) ( (base) + ({core_prefix}{name}_ADDR){addr_shift}) ) = (value));\n"
)
fsw.write("}\n\n")
if "R" in row["type"]:
Expand All @@ -718,7 +719,7 @@ def write_swcode(self, table, out_dir, top):
addr_shift = f" + (addr << {int(log(n_bytes, 2))})"
fsw.write(f"{sw_type} {core_prefix}GET_{name}({addr_arg}) {{\n")
fsw.write(
f" return (*( (volatile {sw_type} *) ( (base) + ({core_prefix}{name}){addr_shift}) ));\n"
f" return (*( (volatile {sw_type} *) ( (base) + ({core_prefix}{name}_ADDR){addr_shift}) ));\n"
)
fsw.write("}\n\n")
fsw.close()
Expand Down
1 change: 0 additions & 1 deletion submodules/UART/hardware/src/iob_uart.v
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,6 @@ module iob_uart #(

// RXDATA Manual logic
assign RXDATA_rready_rd = 1'b1;
assign RXDATA_rvalid_rd = 1'b1;

uart_core uart_core0 (
.clk_i (clk_i),
Expand Down
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