Create iob_axil_split module; Use single axi2axil bridge; Use axil interface for peripherals. Move bootrom to address 0x40000000.
#946
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WIP: axi_interconnect gets stuck while running bootloader.
Add the following python parameters: - name: name of the generated verilog module (we can't have two verilog modules with the same name but different I/Os) - n_inputs: number of input ports - n_outputs: number of output ports - tristate: if true enable dedicated output port for tristate (output enable).
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[0x00000000-0x3FFFFFFF]: Memory (30 bits)
[0x40000000-0x7FFFFFFF]: Bootrom (30 bits)
[0x80000000-0xFFFFFFFF]: Peripherals (uncached) (31 bits)
Also add python parameters for GPIO.