This is a simple Xilinx XDMA example that targets the Xilinx XCAU15P and uses PCIe4.0 x4 XDMA connected to DDR4. There is also an example where the PCIe bus is connected to BRAM form maximum throughput (50Gbps / 6.3GB/s). The board I used (Alinx AXAU15) only had x16 DDR4 and so does not reach the maximum throughput the PCIe4x4 bus is able to reach when connected to DDR.
-
Notifications
You must be signed in to change notification settings - Fork 0
This is a simple Xilinx XDMA example that targets the Xilinx XCAU15P and uses PCIe4.0 x4 to DDR. There is also a BRAM example.
License
Johnsel/xilinx-xcau15p-pcie-gen4
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
This is a simple Xilinx XDMA example that targets the Xilinx XCAU15P and uses PCIe4.0 x4 to DDR. There is also a BRAM example.
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published