New affine address mapper in AGU for non-interleaved data access #1769
lint.yml
on: pull_request
Lint Verilog sources
54s
Check bender vendor up-to-date
17s
Check Opcodes Up-to-Date
8s
Check License headers
8s
Lint YAML Sources
3s
Lint Python Sources
8s
Lint C/C++ Sources
13s
Lint Editorconfig
7s
Matrix: Lint Scala Files
Annotations
10 warnings
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
verible-linter
|
164 Bytes |
|