Fix the insertion of Pipeline Registers in SIMD (#394) #1829
lint.yml
on: push
Lint Verilog sources
40s
Check bender vendor up-to-date
24s
Check Opcodes Up-to-Date
9s
Check License headers
8s
Lint YAML Sources
5s
Lint Python Sources
5s
Lint C/C++ Sources
12s
Lint Editorconfig
5s
Matrix: Lint Scala Files
Annotations
10 warnings
Artifacts
Produced during runtime
Name | Size | |
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verible-linter
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164 Bytes |
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