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* add cut in gemmx datapath * rm comments
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125 changes: 125 additions & 0 deletions
125
hw/chisel_acc/src/main/scala/snax_acc/utils/CustomOperators.scala
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,125 @@ | ||
| package snax_acc.utils | ||
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| import chisel3._ | ||
| import chisel3.util._ | ||
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| /** The definition of -|> / -||> / -|||> connector for decoupled signal it | ||
| * connects leftward Decoupled signal (Decoupled port) and rightward Decoupled | ||
| * signal (Flipped port); and insert one level of pipeline in between to avoid | ||
| * long combinatorial datapath | ||
| */ | ||
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| class DataCut[T <: Data](gen: T, delay: Int) extends Module { | ||
| val io = IO(new Bundle { | ||
| val in = Flipped(Decoupled(gen)) | ||
| val out = Decoupled(gen) | ||
| }) | ||
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| val in = Wire(ValidIO(gen)) | ||
| val out = Wire(ValidIO(gen)) | ||
| val shiftPermission = Wire(Bool()) | ||
| val shiftSuggestion = Wire(Bool()) | ||
| val shift = | ||
| shiftPermission && shiftSuggestion // shift is true when both shiftPermission and shiftSuggestion are true | ||
| in.bits := io.in.bits | ||
| in.valid := io.in.valid | ||
| io.in.ready := shiftPermission | ||
| io.out.valid := out.valid | ||
| io.out.bits := out.bits | ||
| out := ShiftRegister(in, delay, shift) | ||
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| // shiftPermission is true when last item's valid is true and io.out.ready is true or last item's valid is false | ||
| shiftPermission := (out.valid && io.out.ready) || !out.valid | ||
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| val dataInsideShiftRegister = Wire(Bool()) | ||
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| // shiftSuggestion is true when dataInsideShiftRegister is true or input.valid is true | ||
| shiftSuggestion := dataInsideShiftRegister || io.in.valid | ||
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| // When the counter is abbout to overflow, data does not inside the shift register | ||
| val insideCounter = Counter(0 to delay, shift, io.in.valid) | ||
| dataInsideShiftRegister := insideCounter._1 =/= delay.U | ||
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| } | ||
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| object DecoupledCut { | ||
| implicit class BufferedDecoupledConnectionOp[T <: Data]( | ||
| val left: DecoupledIO[T] | ||
| ) { | ||
| // This class defines the implicit class for the new operand -|>,-||>, -|||> for DecoupleIO | ||
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| def -|>( | ||
| right: DecoupledIO[T] | ||
| )(implicit sourceInfo: chisel3.experimental.SourceInfo): DecoupledIO[T] = { | ||
| val buffer = Module( | ||
| new Queue(chiselTypeOf(left.bits), entries = 1, pipe = false) | ||
| ) | ||
| buffer.suggestName("fullCutHalfBandwidth") | ||
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| left <> buffer.io.enq | ||
| buffer.io.deq <> right | ||
| right | ||
| } | ||
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| def -||>( | ||
| right: DecoupledIO[T] | ||
| )(implicit sourceInfo: chisel3.experimental.SourceInfo): DecoupledIO[T] = { | ||
| val buffer = Module( | ||
| new Queue(chiselTypeOf(left.bits), entries = 2, pipe = false) | ||
| ) | ||
| buffer.suggestName("fullCutFullBandwidth") | ||
| left <> buffer.io.enq | ||
| buffer.io.deq <> right | ||
| right | ||
| } | ||
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| def -\>( | ||
| right: DecoupledIO[T] | ||
| )(implicit sourceInfo: chisel3.experimental.SourceInfo): DecoupledIO[T] = { | ||
| val buffer = Module( | ||
| new DataCut(chiselTypeOf(left.bits), delay = 1) | ||
| ) | ||
| buffer.suggestName("dataCut1") | ||
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| left <> buffer.io.in | ||
| buffer.io.out <> right | ||
| right | ||
| } | ||
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| def -\\>( | ||
| right: DecoupledIO[T] | ||
| )(implicit sourceInfo: chisel3.experimental.SourceInfo): DecoupledIO[T] = { | ||
| val buffer = Module( | ||
| new DataCut(chiselTypeOf(left.bits), delay = 2) | ||
| ) | ||
| buffer.suggestName("dataCut2") | ||
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| left <> buffer.io.in | ||
| buffer.io.out <> right | ||
| right | ||
| } | ||
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| def -\\\>( | ||
| right: DecoupledIO[T] | ||
| )(implicit sourceInfo: chisel3.experimental.SourceInfo): DecoupledIO[T] = { | ||
| val buffer = Module( | ||
| new DataCut(chiselTypeOf(left.bits), delay = 3) | ||
| ) | ||
| buffer.suggestName("dataCut3") | ||
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| left <> buffer.io.in | ||
| buffer.io.out <> right | ||
| right | ||
| } | ||
| } | ||
| } | ||
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| object BitsConcat { | ||
| implicit class UIntConcatOp[T <: Bits](val left: T) { | ||
| // This class defines the implicit class for the new operand ++ for UInt | ||
| def ++( | ||
| right: T | ||
| )(implicit sourceInfo: chisel3.experimental.SourceInfo): T = | ||
| Cat(left, right).asInstanceOf[T] | ||
| } | ||
| } |
44 changes: 44 additions & 0 deletions
44
hw/chisel_acc/src/main/scala/snax_acc/utils/DecoupledCat.scala
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| package snax_acc.utils | ||
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| import chisel3._ | ||
| import chisel3.util._ | ||
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| class DecoupledCat2to1[T <: Data](aWidth: Int, bWidth: Int) extends Module{ | ||
| val io = IO(new Bundle { | ||
| val in1 = Flipped(Decoupled(UInt(aWidth.W))) // First decoupled input interface | ||
| val in2 = Flipped(Decoupled(UInt(bWidth.W))) // Second decoupled input interface | ||
| val out = Decoupled(UInt((aWidth + bWidth).W)) // Decoupled output interface | ||
| }) | ||
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| // Combine the bits of in1 and in2, in1 in higher bits | ||
| io.out.bits := Cat(io.in1.bits, io.in2.bits) | ||
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| // Output is valid only when both inputs are valid | ||
| io.out.valid := io.in1.valid && io.in2.valid | ||
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| // Ready is asserted to inputs when the output is ready | ||
| io.in1.ready := io.out.ready && io.out.valid | ||
| io.in2.ready := io.out.ready && io.out.valid | ||
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| } | ||
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| class DecoupledSplit1to2(cWidth: Int, aWidth: Int, bWidth: Int) extends Module { | ||
| require(cWidth == aWidth + bWidth, "cWidth must be the sum of aWidth and bWidth") | ||
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| val io = IO(new Bundle { | ||
| val in = Flipped(Decoupled(UInt(cWidth.W))) // Large decoupled input (c) | ||
| val out1 = Decoupled(UInt(aWidth.W)) // Smaller decoupled output (a) | ||
| val out2 = Decoupled(UInt(bWidth.W)) // Smaller decoupled output (b) | ||
| }) | ||
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| // Split the input bits into two parts | ||
| io.out1.bits := io.in.bits(cWidth - 1, bWidth) // Upper bits go to out1 (a) | ||
| io.out2.bits := io.in.bits(bWidth - 1, 0) // Lower bits go to out2 (b) | ||
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| // Both outputs are valid when the input is valid | ||
| io.out1.valid := io.in.valid | ||
| io.out2.valid := io.in.valid | ||
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| // Input is ready when both outputs are ready | ||
| io.in.ready := io.out1.ready && io.out2.ready | ||
| } |