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It appears that some of the CSRs collide with the physical memory protection address reserved addresses.
11100: 41 11 addi sp, sp, -16 11102: 36 c2 sw a3, 4(sp) 11104: ae 86 mv a3, a1 11106: 92 45 lw a1, 4(sp) 11108: 46 45 lw a0, 80(sp) 1110a: 05 89 andi a0, a0, 1 1110c: b6 42 lw t0, 76(sp) 1110e: a6 42 lw t0, 72(sp) 11110: 96 42 lw t0, 68(sp) 11112: 86 42 lw t0, 64(sp) 11114: f2 52 lw t0, 60(sp) 11116: e2 52 lw t0, 56(sp) 11118: b2 52 lw t0, 44(sp) 1111a: a2 52 lw t0, 40(sp) 1111c: 92 52 lw t0, 36(sp) 1111e: 82 52 lw t0, 32(sp) 11120: f2 42 lw t0, 28(sp) 11122: e2 42 lw t0, 24(sp) 11124: d2 55 lw a1, 52(sp) 11126: 2e c4 sw a1, 8(sp) 11128: 42 56 lw a2, 48(sp) 1112a: 52 46 lw a2, 20(sp) 1112c: 32 c6 sw a2, 12(sp) 1112e: c2 47 lw a5, 16(sp) 11130: 73 90 06 3d csrw pmpaddr32, a3 11134: 73 10 16 3d csrw pmpaddr33, a2 11138: 73 90 35 3d csrw pmpaddr35, a1 1113c: 73 10 47 3d csrw pmpaddr36, a4 11140: 73 d0 00 3c csrwi pmpaddr16, 1 11144: f3 25 30 3c csrr a1, pmpaddr19 11148: 81 45 li a1, 0 1114a: 73 90 55 3c csrw pmpaddr21, a1 1114e: 01 00 nop 11150: 01 00 nop 11152: 01 00 nop 11154: 19 e1 bnez a0, 0x1115a <simple_mult+0x5a> 11156: 6f 00 c0 02 j 0x11182 <simple_mult+0x82> 1115a: 6f 00 40 00 j 0x1115e <simple_mult+0x5e> 1115e: 32 45 lw a0, 12(sp) 11160: a2 45 lw a1, 8(sp) 11162: 73 90 15 3d csrw pmpaddr33, a1 11166: 73 d0 00 3c csrwi pmpaddr16, 1 1116a: f3 25 30 3c csrr a1, pmpaddr19 1116e: 81 45 li a1, 0 11170: 73 90 55 3c csrw pmpaddr21, a1 11174: 01 00 nop 11176: 01 00 nop 11178: 01 00 nop 1117a: 73 10 35 3d csrw pmpaddr35, a0 1117e: 6f 00 80 02 j 0x111a6 <simple_mult+0xa6> 11182: 32 45 lw a0, 12(sp) 11184: a2 45 lw a1, 8(sp) 11186: 73 d0 00 3c csrwi pmpaddr16, 1 1118a: 73 26 30 3c csrr a2, pmpaddr19 1118e: 01 46 li a2, 0 11190: 73 10 56 3c csrw pmpaddr21, a2 11194: 01 00 nop 11196: 01 00 nop 11198: 01 00 nop 1119a: 73 90 15 3d csrw pmpaddr33, a1 1119e: 73 10 35 3d csrw pmpaddr35, a0 111a2: 6f 00 40 00 j 0x111a6 <simple_mult+0xa6> 111a6: 73 d0 00 3c csrwi pmpaddr16, 1 111aa: 73 25 30 3c csrr a0, pmpaddr19 111ae: 01 45 li a0, 0 111b0: 73 10 55 3c csrw pmpaddr21, a0 111b4: 01 00 nop 111b6: 01 00 nop 111b8: 01 00 nop 111ba: 41 01 addi sp, sp, 16 111bc: 82 80 ret
Not a priority right now, but something to be aware of?
The text was updated successfully, but these errors were encountered:
Oof really? That wasn't on the list they had or did they just add it hmm...
Sorry, something went wrong.
hw: Fix memory consistency between int and FP datapaths (#90)
1a0ff31
* hw: Fix load-store consistency between int and FP datapaths * hw: Block CAQ handshake on non-acc stalls * hw: Ensure FP reads collide with integer atomics in CAQ * hw: Add isochronous cut to CAQ response channel * hw: Prevent multiple CAQ responses when using FREP * hw: Tune defaults for CAQ parameters, covering TCDM * sw: Add synthetic tests for CAQ races and CAQ-FREP interaction * sw/math: Remove FP-INT memory-consistency patches * sw: Sharpen CAQ tests, ensure full failure on pre-CAQ HW * fesvr: Patch to not use deprecated `ucontext.h` * ci: Disable FlashAttention-2 kernel --------- Co-authored-by: Luca Colagrande <[email protected]>
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It appears that some of the CSRs collide with the physical memory protection address reserved addresses.
Not a priority right now, but something to be aware of?
The text was updated successfully, but these errors were encountered: