GitHub - Klamath233/lianliankan-verilog: 152 Final Project

Name		Name	Last commit message	Last commit date
Latest commit History 33 Commits
.gitignore		.gitignore
board.v		board.v
board_test.v		board_test.v
card.v		card.v
card_array.v		card_array.v
card_array_test.v		card_array_test.v
card_test.v		card_test.v
clk_div_to_1k.v		clk_div_to_1k.v
clk_div_to_1k_test.v		clk_div_to_1k_test.v
clk_div_to_one.v		clk_div_to_one.v
clk_div_to_one_test.v		clk_div_to_one_test.v
clock_module.v		clock_module.v
cursor.v		cursor.v
cursor_test.v		cursor_test.v
debounce.v		debounce.v
debounce.vhd		debounce.vhd
functional_test.v		functional_test.v
input_module.v		input_module.v
matcher.v		matcher.v
nexys3.ucf		nexys3.ucf
top.v		top.v
vga.v		vga.v