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RVVM is a virtual machine / emulator for RISC-V guests, which emphasizes on performance, security, lean code and portability. It already runs a lot of guest operating systems, including Linux, Haiku, FreeBSD, OpenBSD, etc. It also aims to run RISC-V applications on a foreign-arch host without full OS guest & isolation (Userland emulation).
RVVM supports most host operating systems, including Linux, *BSD, Mac OS, Windows, Haiku. It works pretty much on any POSIX/Win32 host. It even works in WASM, albeit slowly due to lack of JIT, and on DOS (via HX Extender)
Emulation performance is higher than that of QEMU TCG, thanks to a tracing RVJIT with better designed IR and less guest instructions splitting, and usage of hardware floating-point unit. RVJIT supports x86_64, ARM64 backends, as well as a reference RISCV64 backend. Hosts without a JIT backend are using a slower, albeit still pretty optimized and portable interpreter.
Support for KVM on real RISC-V hardware is planned, but requires a board with Hypervisor extension for this development. In the meantime, a special kernel module is being developed to match native speeds without a Hypervisor-capable hardware: https://github.com/LekKit/shadow_pgt. It already allows to reach native execution speed on a VisionFive 2 in many benchmarks, but a lot of work still has to be done. This kernel module should also allow speeding up guests on foreign-architecture hosts.
To prevent theoretical VM escape vulnerabilities from being exploited, kernel-level isolation is implemented via means of seccomp on Linux and pledge() on OpenBSD. Additionally, any capabilities are dropped and the process switches into user nobody, on any POSIX OS. In future, more means of isolation can be implemented for Windows and other *BSD hosts.
Other means of enhancing security include strict codestyle & compiler warning policies, extensive static analysis and use of sanitizers. Most codebase infrastructure is fuzzed locally.
- Fully spec-compliant rv64imafdcb instruction set, Zkr/Zicbom/Zicboz/Sstc extensions, riscv32 mode
- Tracing JIT with x86_64, ARM64, RISC-V backends - Faster than QEMU TCG
- SMP (multi-core) support, ACLINT MSWI/MTIMER, PLIC interrupt controller
- PCIe Express bus
- NVMe storage drives, TRIM support (Deallocate space on host), fast multi-threaded IO
- Realtek RTL8169 10 Gbps NIC, userland TCP/IP networking stack with epoll/kqueue support
- Framebuffer graphics (simplefb / EFIFB), VM display GUI
- I2C-HID input devices, host cursor passthrough/grab modes
- VFIO PCIe passthrough on Linux hosts (Allows GPU acceleration, access to host USB devices via XHCI passthrough)
- NS16550A UART terminal
- OpenCores I2C controller (Found on HiFive SoCs)
- Goldfish & DS1742 Real-time clock
- Syscon poweroff/reset
- Firmware MTD flash device
- SiFive GPIO
- Construct multiple virtual machines in one process
- Per-machine options (Amount of RAM, cores, JIT cache)
- HID, Framebuffer, Chardev APIs for custom GUI/Terminals
- MMIO, DMA, interrupt APIs for implementing new devices
- Device Tree generation
- Userland emulation API (Run RISC-V thread contexts inside a host process)
- PS2 input devices
- IDE ATA storage disk
- OpenCores Ethernet NIC (10 Mbps)
- Linux TAP networking backend (See #84)
- RVJIT backends for i386, arm32, riscv32 (Can only accelerate riscv32 guests, arm32 backend unmaintained)