Filtering analog signal with VDHL
This project shows a possible implementation of a FIR digital filter used to filter an analog signal. VHDL was the language used, in conjunction with the FPGA Nexys 3 - Spartan 6. The filter consists of 21 coefficients, which were obtained through Matlab software. The transmission between the Nexys 3 and the laptop was implemented by the UART module.
In the file called "scalambrin_luca_report.pdf" you will find a report presented for the project, which is written in Spanish language.