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Address Jerome's comments
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Add __maybe_unused qualifier
Use upper case for acronyms
Conditional checks for HiKey specific code
Improve print format for peri and cell IDs
Add config to .travis.yml
Remove \n from DMSG

Signed-off-by: Victor Chong <[email protected]>
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Victor Chong committed Jul 21, 2016
1 parent 49d8c28 commit 60ad160
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Showing 3 changed files with 39 additions and 31 deletions.
1 change: 1 addition & 0 deletions .travis.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,7 @@ script:
- $make PLATFORM=hikey
- $make PLATFORM=hikey CFG_ARM64_core=y
- $make PLATFORM=hikey CFG_ARM64_core=y CFG_TEE_TA_LOG_LEVEL=4 DEBUG=1
- $make PLATFORM=hikey CFG_ARM64_core=y CFG_TEE_TA_LOG_LEVEL=4 DEBUG=1 CFG_PL061=y CFG_PL022=y

# Mediatek mt8173 EVB
- $make PLATFORM=mediatek-mt8173 CFG_ARM64_core=y
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2 changes: 2 additions & 0 deletions core/arch/arm/plat-hikey/platform_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,8 @@
#ifndef PLATFORM_CONFIG_H
#define PLATFORM_CONFIG_H

#define PLATFORM_hikey 1

/* Make stacks aligned to data cache line length */
#define STACK_ALIGNMENT 64

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67 changes: 36 additions & 31 deletions core/drivers/pl022_spi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -33,10 +33,11 @@
#include <io.h>
#include <kernel/panic.h>
#include <kernel/tee_time.h>
#include <platform_config.h>
#include <trace.h>
#include <util.h>

/* spi register offsets */
/* SPI register offsets */
#define SSPCR0 0x000
#define SSPCR1 0x004
#define SSPDR 0x008
Expand All @@ -48,10 +49,12 @@
#define SSPICR 0x020
#define SSPDMACR 0x024

/* hikey extensions */
#ifdef PLATFORM_hikey
/* HiKey extensions */
#define SSPTXFIFOCR 0x028
#define SSPRXFIFOCR 0x02C
#define SSPB2BTRANS 0x030
#endif

/* test registers */
#define SSPTCR 0x080
Expand All @@ -69,7 +72,7 @@
#define SSPPCellID2 0xFF8
#define SSPPCellID3 0xFFC

/* spi register masks */
/* SPI register masks */
#define SSPCR0_SCR SHIFT_U32(0xFF, 8)
#define SSPCR0_SPH SHIFT_U32(1, 7)
#define SSPCR0_SPH1 SHIFT_U32(1, 7)
Expand Down Expand Up @@ -147,7 +150,7 @@
#define MASK_12 0xFFF
#define MASK_8 0xFF
#define MASK_4 0xF
/* spi register masks */
/* SPI register masks */

#define SSP_CPSDVR_MAX 254
#define SSP_CPSDVR_MIN 2
Expand Down Expand Up @@ -308,8 +311,8 @@ static void pl022_rx16(struct spi_chip *chip, uint16_t *rdat,

static void pl022_print_peri_id(struct pl022_data *pd __maybe_unused)
{
DMSG("Expected: 0x 22 10 #4 0");
DMSG("Read: 0x %x %x %x %x\n",
DMSG("Expected: 0x 22 10 ?4 00");
DMSG("Read: 0x %02x %02x %02x %02x",
read32(pd->base + SSPPeriphID0),
read32(pd->base + SSPPeriphID1),
read32(pd->base + SSPPeriphID2),
Expand All @@ -318,8 +321,8 @@ static void pl022_print_peri_id(struct pl022_data *pd __maybe_unused)

static void pl022_print_cell_id(struct pl022_data *pd __maybe_unused)
{
DMSG("Expected: 0x 0D F0 05 B1");
DMSG("Read: 0x %x %x %x %x\n",
DMSG("Expected: 0x 0d f0 05 b1");
DMSG("Read: 0x %02x %02x %02x %02x",
read32(pd->base + SSPPCellID0),
read32(pd->base + SSPPCellID1),
read32(pd->base + SSPPCellID2),
Expand All @@ -337,8 +340,10 @@ static void pl022_sanity_check(struct pl022_data *pd)
assert(pd->mode <= SPI_MODE3);
assert(pd->data_size_bits == 8 || pd->data_size_bits == 16);

DMSG("SSPB2BTRANS: Expected: 0x2. Read: 0x%x\n",
#ifdef PLATFORM_hikey
DMSG("SSPB2BTRANS: Expected: 0x2. Read: 0x%x",
read32(pd->base + SSPB2BTRANS));
#endif
pl022_print_peri_id(pd);
pl022_print_cell_id(pd);
}
Expand Down Expand Up @@ -385,26 +390,26 @@ static void pl022_calc_clk_divisors(struct pl022_data *pd,
if (freq1 >= freq2) {
*cpsdvr = tmp_cpsdvr1;
*scr = tmp_scr1;
DMSG("speed: requested: %u, closest1: %u\n",
DMSG("speed: requested: %u, closest1: %u",
pd->speed_hz, freq1);
} else {
*cpsdvr = tmp_cpsdvr2;
*scr = tmp_scr2;
DMSG("speed: requested: %u, closest2: %u\n",
DMSG("speed: requested: %u, closest2: %u",
pd->speed_hz, freq2);
}
DMSG("cpsdvr: %u (0x%x), scr: %u (0x%x)\n",
DMSG("CPSDVR: %u (0x%x), SCR: %u (0x%x)",
*cpsdvr, *cpsdvr, *scr, *scr);
}

static void pl022_flush_fifo(struct pl022_data *pd)
{
uint32_t rdat;
uint32_t __maybe_unused rdat;

do {
while (read32(pd->base + SSPSR) & SSPSR_RNE) {
rdat = read32(pd->base + SSPDR);
DMSG("rdat: 0x%x\n", rdat);
DMSG("rdat: 0x%x", rdat);
}
} while (read32(pd->base + SSPSR) & SSPSR_BSY);
}
Expand Down Expand Up @@ -433,67 +438,67 @@ void pl022_configure(struct pl022_data *pd)
/* configure ssp based on platform settings */
switch (pd->mode) {
case SPI_MODE0:
DMSG("SPI_MODE0\n");
DMSG("SPI_MODE0");
mode = PL022_SPI_MODE0;
break;
case SPI_MODE1:
DMSG("SPI_MODE1\n");
DMSG("SPI_MODE1");
mode = PL022_SPI_MODE1;
break;
case SPI_MODE2:
DMSG("SPI_MODE2\n");
DMSG("SPI_MODE2");
mode = PL022_SPI_MODE2;
break;
case SPI_MODE3:
DMSG("SPI_MODE3\n");
DMSG("SPI_MODE3");
mode = PL022_SPI_MODE3;
break;
default:
EMSG("Invalid spi mode: %u\n", pd->mode);
EMSG("Invalid SPI mode: %u", pd->mode);
panic();
}

switch (pd->data_size_bits) {
case 8:
DMSG("Data size: 8\n");
DMSG("Data size: 8");
data_size = PL022_DATA_SIZE8;
break;
case 16:
DMSG("Data size: 16\n");
DMSG("Data size: 16");
data_size = PL022_DATA_SIZE16;
break;
default:
EMSG("Unsupported data size: %u bits\n", pd->data_size_bits);
EMSG("Unsupported data size: %u bits", pd->data_size_bits);
panic();
}

if (pd->loopback) {
DMSG("Starting in loopback mode!\n");
DMSG("Starting in loopback mode!");
lbm = SSPCR1_LBM_YES;
} else {
DMSG("Starting in regular (non-loopback) mode!\n");
DMSG("Starting in regular (non-loopback) mode!");
lbm = SSPCR1_LBM_NO;
}

DMSG("set serial clock rate (scr), spi mode (phase and clock)\n");
DMSG("set frame format (spi) and data size (8- or 16-bit)\n");
DMSG("set Serial Clock Rate (SCR), SPI mode (phase and clock)");
DMSG("set frame format (SPI) and data size (8- or 16-bit)");
io_mask16(pd->base + SSPCR0, SHIFT_U32(scr, 8) | mode | SSPCR0_FRF_SPI |
data_size, MASK_16);

DMSG("set master mode, disable ssp, set loopback mode\n");
DMSG("set master mode, disable SSP, set loopback mode");
io_mask8(pd->base + SSPCR1, SSPCR1_SOD_DISABLE | SSPCR1_MS_MASTER |
SSPCR1_SSE_DISABLE | lbm, MASK_4);

DMSG("set clock prescale\n");
DMSG("set clock prescale");
io_mask8(pd->base + SSPCPSR, cpsdvr, SSPCPSR_CPSDVR);

DMSG("disable interrupts\n");
DMSG("disable interrupts");
io_mask8(pd->base + SSPIMSC, 0, MASK_4);

DMSG("set cs gpio dir to out\n");
DMSG("set CS GPIO dir to out");
gpio_set_direction(pd->cs_gpio_pin, GPIO_DIR_OUT);

DMSG("pull cs high\n");
DMSG("pull CS high");
gpio_set_value(pd->cs_gpio_pin, GPIO_LEVEL_HIGH);
}

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