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Rk322x #1666

Merged
merged 3 commits into from
Jul 25, 2017
Merged

Rk322x #1666

merged 3 commits into from
Jul 25, 2017

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TonyXie06
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add plat-rockchip support into optee_os, the SoC is RK322X.

#define CRU_SNDRST_VAL 0xeca8
#define PLLS_SLOW_MODE 0x11030000

#define CORE_SOFT_RESET(core) (0x100010 << (core))
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Please use SHIFT_U32() (from <util.h.>, like SHIFT_U32(0x100010, (core)) instead
Same for the other defines below.

read_actlr r0
orr r0, r0, #ACTLR_SMP
write_actlr r0

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bx lr missing?


#define SGRF_SOC_CON(n) ((n) * 4)
#define DDR_SGRF_DDR_CON(n) ((n) * 4)
#define DDR_RGN0_NS ((1 << 30) | (0 << 14))
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Please use the BIT32() macro from <util.h> instead, like (BIT32(30) | BIT32(14))

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Hi, there is (0 << 14), not (1 << 14).
I would like to set bit14 as 0. For obvious, so I use (0 << 14). Should I use "#define DDR_RGN0_NS BIT(30)" ?

/* Make stacks aligned to data cache line length */
#define STACK_ALIGNMENT 64

#ifdef ARM64
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Since this is a ARMv7 platform, ARM64 will never be defined so this isn't needed.

#include <tee/entry_std.h>
#include <tee/entry_fast.h>

#define CORE_WFE_MSK(core) (0x02 << (core))
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Use SHIFT_U32() instead

}

int psci_cpu_on(uint32_t core_idx, uint32_t entry,
uint32_t context_id __attribute__((unused)))
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Please use the __unused define from <compiler.h>

write32(LOCK_TAG, isram_base + LOCK_ADDR_OFFSET);
dsb();

__asm("sev");
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Please define a sev() function in <arm32.h> and use that instead.


/* in order to sync with secondary up cpu */
cache_op_inner(DCACHE_CLEAN_INV, NULL, 0);
dsb();
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The function doing the clean invalidate ends with:

dsb
isb

just before returning so these two should not be needed.

isb();

while (1)
__asm("wfi");
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Please define a wfi() function in <arm32.h> and use that instead.

@@ -86,7 +86,7 @@ static int serial8250_uart_getchar(struct serial_chip *chip)
/* Transmit FIFO is empty, waiting again */
;
}
return read8(base + UART_RHR);
return read32(base + UART_RHR);
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I wonder if we should mask the result with 0xff just to make sure that this function doesn't return unexpected bits.

@jenswi-linaro
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Acked-by: Jens Wiklander <[email protected]>
but I'd like feedback from some of the maintainers of platforms that use the serial8250_uart driver.
@sorenb-xlnx @glneo Ping?

@jforissier
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but I'd like feedback from some of the maintainers of platforms that use the serial8250_uart driver.

Agreed, ideally I'd like some Tested-by's on the driver patch before merging it.

vaddr_t va_base = (vaddr_t)phys_to_virt_io(GRF_BASE);

wfei_mask = CORE_WFE_I_MSK(core);
while (!(read32(va_base + GRF_CPU_STATUS1) & wfei_mask) && loop < 500) {
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What happens if loop reaches 500 and the condition is still not met? Should you be returning an error for the caller to deal with the situation? Or assert()?

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I discussed with my team mate, we thought it is better to print error message and return an error code, then give up cpu up this time.

#ifndef DELAY_H
#define DELAY_H

#include <arm32.h>
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Replace with #include <arm.h> and move this file to core/arch/arm/include/kernel/. Other platforms will likely need this sooner or later.

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Sorry for my clerical error:"while (read_cntfrq() - start <= target)" , it should be read_cntpct(). I will fix this.

}
}

static int core_held_in_reset(uint32_t core)
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s/int/bool/

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pardon? I can't get what you mean.

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you mean this function should return a bool type? like this: static bool core_held_in_reset(uint32_t core) ?

@sorenb-xlnx
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@jenswi-linaro: Zynqmp uses a Cadence UART (drivers/cdns_uart.c). I don't think we have any dependency on the 8250.

@jforissier
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We need T-b for platforms rpi3, mtk-mt8173 and ti-<something>, if I'm not mistaken.

@igoropaniuk
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igoropaniuk commented Jul 7, 2017

@jforissier right,

$ grep -r "#include <drivers/serial8250_uart.h>" .
./documentation/porting_guidelines.md:#include <drivers/serial8250_uart.h>
./core/arch/arm/plat-mediatek/main.c:#include <drivers/serial8250_uart.h>
./core/arch/arm/plat-rpi3/main.c:#include <drivers/serial8250_uart.h>
./core/arch/arm/plat-ti/main.c:#include <drivers/serial8250_uart.h>
./core/drivers/serial8250_uart.c:#include <drivers/serial8250_uart.h>

I can test on RPi3 and TI-AM57xx today

@igoropaniuk
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igoropaniuk commented Jul 7, 2017

@jforissier @jenswi-linaro
Successfully receiving SW output on RPi3, no issues found (checked on e847d4f)

Tested-by: Igor Opaniuk <[email protected]> (serial8250_uart, RPi3)

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Just 2 minor comments, in any case:
Reviewed-by: Jerome Forissier <[email protected]>


val = read32(va_base + CRU_SOFTRST_CON(0));

return !!(val & CORE_HELD_IN_RESET(core));
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!! is not needed since you're returning bool now

loop++;
}

return !!(read32(va_base + GRF_CPU_STATUS1) & wfei_mask);
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Here also !! is useless

@jenswi-linaro
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@sorenb-xlnx thanks, my mistake.

@igoropaniuk
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igoropaniuk commented Jul 10, 2017

The same for TI-AM57xx (checked only SW output over UART):

Tested-by: Igor Opaniuk <[email protected]> (serial8250_uart, TI-AM57xx)

@TonyXie06
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Hi, Jens, do you approve above update ?
If nothing complains, I'd like to add another 2 patches to support system suspend which is relay on above commits. Should I append 2 patches after above commits in current pull request ?


#include <arm.h>

static inline void udelay(uint32_t us)
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This function looks a bit large to be an inline function.

* POSSIBILITY OF SUCH DAMAGE.
*/

#ifndef DELAY_H
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Use __KERNEL_DELAY_H instead

uint64_t start, target;

start = read_cntpct();
target = read_cntfrq() / 1000000 * us;
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Can this overflow?

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Agreed, I think use 1000000ULL can fix this.

if (!core_held_in_reset(core_idx)) {
wfei = wait_core_wfe_i(core_idx);
if (!wfei) {
EMSG("Can't wait cpu%d wfei before softrst", core_idx);
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@jenswi-linaro jenswi-linaro Jul 13, 2017

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core_idx is an uint32_t so replace %d with %" PRIu32 "
Please fix the EMSG() below also.

@jenswi-linaro
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I think it's better to only add fixes to this pull request. Once we've merged this create a new pull request with the new stuff.

@jenswi-linaro
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Acked-by: Jens Wiklander <[email protected]>

Please fixup all the commits. You can apply my tag to all the commits, but I think we should give @jforissier another chance to approve it.

@TonyXie06
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Hi, jens, do you mean I should fixup 3th~11th commits into 1st, 2nd commits, only 2 commit left finally and use git push -f ?(Sorry that I am not fimiliar with pull request work flow)

@jenswi-linaro
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Yes, I guess it will be around 3 commits in the end.
The 8250 commit
The delay commit
and the plat-rockchip commit

@TonyXie06
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Hey, Jens, this weekend, I found MrVan's patches for plat-imx PSCI was merged a few days ago, I read it and there are something good for me to follow, so I want to have a update before fixup my commits. I will do a update later.

@TonyXie06
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Hi, jens, some opinions ? Should I fixup commits ?

@jenswi-linaro
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Please fixup and I'll review it again.

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Looks good to me. For all 3 commits:
Acked-by: Jerome Forissier <[email protected]>

@TonyXie06 you can also apply @igoropaniuk's Tested-by's to the UART commit. Could someone test on mtk-mt8173?

#define PLAT_ROCKCHIP_COMMON_H

/* For SMP cpu bootup, they are common for rockchip platforms */
#define LOCK_TAG 0xDEADBEAF
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Is it really 0xDEADBEAF and not 0xDEADBEEF?

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Yes, really.

@TonyXie06
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Jforissier, thank you for your approve and remind, I will apply tags after Jens review and approve.

@jenswi-linaro
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Acked-by: Jens Wiklander <[email protected]>

Due to hardware design, some platforms can't access the peripheral IO
registers once a byte(8-bit) but once a word(32-bit). Obviously, using
32-bit accesses to the registers is more flexible for other plaforms
to use serial8250 uart.

Signed-off-by: Joseph Chen <[email protected]>
Acked-by: Jerome Forissier <[email protected]>
Acked-by: Jens Wiklander <[email protected]>
Tested-by: Igor Opaniuk <[email protected]> (serial8250_uart, TI-AM57xx)
Using ARM Generic Timer to support time delay, make sure CNTFRQ
register has been initialized before use.

Signed-off-by: Joseph Chen <[email protected]>
Acked-by: Jerome Forissier <[email protected]>
Acked-by: Jens Wiklander <[email protected]>
Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores ARM SoCs.

plat-rockchip support features:
1.Support SMP cpu boot up and power down;
2.Support system reset;
3.Support GIC driver initialization.

make PLATFORM=rockchip-rk322x

Signed-off-by: Joseph Chen <[email protected]>
Acked-by: Jerome Forissier <[email protected]>
Acked-by: Jens Wiklander <[email protected]>
@TonyXie06
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tags applied.
I learned and will be efficient next time.

@jforissier jforissier merged commit 7176a0b into OP-TEE:master Jul 25, 2017
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@TonyXie06 thanks for your contribution!

One thing I notice only now: would you mind updating README.md, .travis.yml, and (optionally) MAINTAINERS.md? See for instance how it's done in https://github.com/OP-TEE/optee_os/pull/1714/files.

fengguang pushed a commit to 0day-ci/linux that referenced this pull request Aug 22, 2017
…nux/kernel/git/mmind/linux-rockchip into next/dt

Pull "Rockchip dts32 changes for 4.14" from Heiko Stübner:

Removal of the deprectated num-slots property from all Rockchip dw-mmc
nodes. The rv1108 gains support for sd-cards on the evaluation board and
the general nodes get a bit of cosmetic. On rk3288 the evb gains support
saradc and the adc-key connected to it while some more boards also get
their mali gpu enabled (fennec, evb, tinker).

The biggest set of changes can be found on the rk3228/rk3229 combo this
time. It gets core support for efuse, sdmmc, sdio, io-domans and spdif
as well as a separate rk3229.dtsi that will keep the slight differences
between the two brothers rk3228/rk3229. The evaluation board also gets
some attention and abled nodes (regulators, io-domains, emmc, tsadc keys)

But I think the most interesting change is the cpu enable-method for it.
Instead of using the older in-kernel method, we're now also moving to
handling this in firmware via the psci interface on 32bit Rockchip socs.
In a recently merged pull request [0] support for the rk3228/rk3229 was
added to OP-TEE including the psci support and it seems supporting other
32bit Rockchip socs that way is also planned for the future.

[0] OP-TEE/optee_os#1666

* tag 'v4.14-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (23 commits)
  ARM: dts: rockchip: fix property-ordering in rv1108 mmc nodes
  ARM: dts: rockchip: enable sdmmc for rv1108 evb
  ARM: dts: rockchip: add efuse device node for rk3228
  ARM: dts: rockchip: add gpio power-key for rk3229-evb
  ARM: dts: rockchip: enable tsadc for rk3229-evb
  ARM: dts: rockchip: enable eMMC for rk3229-evb
  ARM: dts: rockchip: enable io-domain for rk3229-evb
  ARM: dts: rockchip: add cpu-supply property for cpu node of rk3229-evb
  ARM: dts: rockchip: add regulator nodes for rk3229-evb
  ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoC
  ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoC
  ARM: dts: rockchip: add cpu enable method for rk3228 SoC
  ARM: dts: rockchip: remove num-slots from all platforms
  ARM: dts: rockchip: Add io-domain node for rk3228
  ARM: dts: rockchip: add basic dtsi file for RK3229 SoC
  ARM: dts: rockchip: enable adc key for rk3288-evb
  ARM: dts: rockchip: enable saradc for rk3288-evb
  ARM: dts: rockchip: enable ARM Mali GPU on rk3288-fennec
  ARM: dts: rockchip: enable ARM Mali GPU on rk3288-evb
  ARM: dts: rockchip: enable ARM Mali GPU on rk3288-tinker
  ...
ijc pushed a commit to ijc/devicetree-conversion-state-v1 that referenced this pull request Sep 17, 2017
…nux/kernel/git/mmind/linux-rockchip into next/dt

Pull "Rockchip dts32 changes for 4.14" from Heiko Stübner:

Removal of the deprectated num-slots property from all Rockchip dw-mmc
nodes. The rv1108 gains support for sd-cards on the evaluation board and
the general nodes get a bit of cosmetic. On rk3288 the evb gains support
saradc and the adc-key connected to it while some more boards also get
their mali gpu enabled (fennec, evb, tinker).

The biggest set of changes can be found on the rk3228/rk3229 combo this
time. It gets core support for efuse, sdmmc, sdio, io-domans and spdif
as well as a separate rk3229.dtsi that will keep the slight differences
between the two brothers rk3228/rk3229. The evaluation board also gets
some attention and abled nodes (regulators, io-domains, emmc, tsadc keys)

But I think the most interesting change is the cpu enable-method for it.
Instead of using the older in-kernel method, we're now also moving to
handling this in firmware via the psci interface on 32bit Rockchip socs.
In a recently merged pull request [0] support for the rk3228/rk3229 was
added to OP-TEE including the psci support and it seems supporting other
32bit Rockchip socs that way is also planned for the future.

[0] OP-TEE/optee_os#1666

* tag 'v4.14-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (23 commits)
  ARM: dts: rockchip: fix property-ordering in rv1108 mmc nodes
  ARM: dts: rockchip: enable sdmmc for rv1108 evb
  ARM: dts: rockchip: add efuse device node for rk3228
  ARM: dts: rockchip: add gpio power-key for rk3229-evb
  ARM: dts: rockchip: enable tsadc for rk3229-evb
  ARM: dts: rockchip: enable eMMC for rk3229-evb
  ARM: dts: rockchip: enable io-domain for rk3229-evb
  ARM: dts: rockchip: add cpu-supply property for cpu node of rk3229-evb
  ARM: dts: rockchip: add regulator nodes for rk3229-evb
  ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoC
  ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoC
  ARM: dts: rockchip: add cpu enable method for rk3228 SoC
  ARM: dts: rockchip: remove num-slots from all platforms
  ARM: dts: rockchip: Add io-domain node for rk3228
  ARM: dts: rockchip: add basic dtsi file for RK3229 SoC
  ARM: dts: rockchip: enable adc key for rk3288-evb
  ARM: dts: rockchip: enable saradc for rk3288-evb
  ARM: dts: rockchip: enable ARM Mali GPU on rk3288-fennec
  ARM: dts: rockchip: enable ARM Mali GPU on rk3288-evb
  ARM: dts: rockchip: enable ARM Mali GPU on rk3288-tinker
  ...

[ upstream commit: fc244e3 ]
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