ChiselAIA是RISC-V高级中断架构(Advanced Interrupt Architecture, AIA)的开源Chisel实现。 现有的开源AIA实现主要是用Verilog编写的相关工作。 ChiselAIA旨在将Chisel敏捷开发的方法应用于AIA的实现。
ChiselAIA
is an open-sourced Chisel implementation of the RISC-V Advanced Interrupt Architecture (AIA).
Existing open-sourced AIA implementations are primarily written in Verilog (see Related Works).
ChiselAIA
aims to leverage Chisel's agile development methodology for AIA implementation.
该实现包括:
- Incoming Message-Signaled Interrupt Controller (IMSIC): src/main/scala/IMSIC.scala
- Advanced Platform-Level Interrupt Controller (APLIC): src/main/scala/APLIC.scala
- 支持消息信号中断(message-signaled interrupt, MSI)传递模式(domaincfg.DM=1), 该模式下,APLIC将线中断转换为MSI并发送给IMSIC
- 暂不支持直接传递模式(domaincfg.DM=0)
- IMSIC和APLIC的单元测试: test/*/main.py
更多信息,请参阅文档。
This implementation includes:
- Incoming Message-Signaled Interrupt Controller (IMSIC):
src/main/scala/IMSIC.scala
- Advanced Platform-Level Interrupt Controller (APLIC):
src/main/scala/APLIC.scala
- Supports message-signaled interrupt (MSI) delivery mode (domaincfg.DM=1), where the APLIC converts wired interrupts to MSI and sends them to IMSIC
- Direct delivery mode is currently not supported (domaincfg.DM=0)
- The unit tests for IMSIC and APLIC:
test/*/main.py
For more detailed information, please refer to the documentation.
依赖均由nix
管理。
如果你还没有安装nix
,可以参考nix
官方文档进行安装。
Dependencies are managed by nix
.
If you haven't installed nix
, you can refer to nix official installation.
# 进入nix shell(推荐使用direnv自动进入nix shell):
# Enter the nix shell (direnv is recommended for auto entering the nix shell):
nix-shell
# 生成Verilog并运行单元测试:
# Generate Verilog and run unit tests:
make -j
# 显示帮助信息:
# Display help information:
h
- OpenXiangShan/OpenAIA
- 采用Verilog(Implemented in Verilog)
- 支持IMSIC(IMSIC supported)
- 不支持APLIC(APLIC not supported)
- zero-day-labs/riscv-aia
- 采用Verilog(Implemented in Verilog)
- 支持IMSIC(IMSIC supported)
- 支持多种IMSIC微架构:原生、岛式和嵌入式(Multiple IMSIC microarchitectures available: vanilla, island and embedded)
- 支持APLIC(APLIC supported)