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timing(cmo_sink_node): optimize CMO_node timing #260

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merged 2 commits into from
Oct 8, 2024
Merged

timing(cmo_sink_node): optimize CMO_node timing #260

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timing(cmo_sink_node): optimize CMO_node timing
Sep 25, 2024
8dda445
timing(cmo_sink_node): fix delaying one cycle for cmoReq by PipelineC…
Oct 8, 2024
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10 changes: 6 additions & 4 deletions src/main/scala/coupledL2/CoupledL2.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ package coupledL2

import chisel3._
import chisel3.util._
import utility.{FastArbiter, ParallelMax, ParallelPriorityMux, Pipeline, RegNextN, XSPerfAccumulate}
import utility.{FastArbiter, ParallelMax, ParallelPriorityMux, Pipeline, RegNextN, XSPerfAccumulate, PipelineConnect}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink._
Expand Down Expand Up @@ -446,9 +446,11 @@ abstract class CoupledL2Base(implicit p: Parameters) extends LazyModule with Has

cmo_sink_node match {
case Some(x) =>
slice.io.cmoReq.valid := x.in.head._1.valid && bank_eq(x.in.head._1.bits.address >> offsetBits, i, bankBits)
slice.io.cmoReq.bits := x.in.head._1.bits
x.in.head._1.ready := slice.io.cmoReq.ready
val cmoReq = Wire(DecoupledIO(new CMOReq))
cmoReq.valid := x.in.head._1.valid && bank_eq(x.in.head._1.bits.address >> offsetBits, i, bankBits)
cmoReq.bits := x.in.head._1.bits
x.in.head._1.ready := cmoReq.ready
PipelineConnect(cmoReq, slice.io.cmoReq, slice.io.cmoReq.ready, false.B, false.B)
case None =>
slice.io.cmoReq.valid := false.B
slice.io.cmoReq.bits.opcode := 0.U
Expand Down
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