Directory:fix perfCounter bug, match resp_bits with right valid and r…

…eplacerInfo (#161)
OpenXiangShan · Jan 3, 2024 · 449e4a8 · 449e4a8
1 parent 6017c82
commit 449e4a8
Showing 1 changed file with 16 additions and 16 deletions.
diff --git a/src/main/scala/huancun/noninclusive/Directory.scala b/src/main/scala/huancun/noninclusive/Directory.scala
@@ -317,33 +317,33 @@ class Directory(implicit p: Parameters)
   assert(dirReadPorts == 1)
   val req_r = RegEnable(req.bits, req.fire)
   XSPerfAccumulate(cacheParams, "selfdir_A_req", req_r.replacerInfo.channel(0) && resp.valid)
-  XSPerfAccumulate(cacheParams, "selfdir_A_hit", req_r.replacerInfo.channel(0) && resp.valid && resp.bits.self.hit)
+  XSPerfAccumulate(cacheParams, "selfdir_A_hit", RegNext(req_r.replacerInfo.channel(0) && resp.valid) && resp.bits.self.hit)
   XSPerfAccumulate(cacheParams, "selfdir_B_req", req_r.replacerInfo.channel(1) && resp.valid)
-  XSPerfAccumulate(cacheParams, "selfdir_B_hit", req_r.replacerInfo.channel(1) && resp.valid && resp.bits.self.hit)
+  XSPerfAccumulate(cacheParams, "selfdir_B_hit", RegNext(req_r.replacerInfo.channel(1) && resp.valid) && resp.bits.self.hit)
   XSPerfAccumulate(cacheParams, "selfdir_C_req", req_r.replacerInfo.channel(2) && resp.valid)
-  XSPerfAccumulate(cacheParams, "selfdir_C_hit", req_r.replacerInfo.channel(2) && resp.valid && resp.bits.self.hit)
+  XSPerfAccumulate(cacheParams, "selfdir_C_hit", RegNext(req_r.replacerInfo.channel(2) && resp.valid) && resp.bits.self.hit)
 
-  XSPerfAccumulate(cacheParams, "selfdir_dirty", resp.valid && resp.bits.self.dirty)
-  XSPerfAccumulate(cacheParams, "selfdir_TIP", resp.valid && resp.bits.self.state === TIP)
-  XSPerfAccumulate(cacheParams, "selfdir_BRANCH", resp.valid && resp.bits.self.state === BRANCH)
-  XSPerfAccumulate(cacheParams, "selfdir_TRUNK", resp.valid && resp.bits.self.state === TRUNK)
-  XSPerfAccumulate(cacheParams, "selfdir_INVALID", resp.valid && resp.bits.self.state === INVALID)
+  XSPerfAccumulate(cacheParams, "selfdir_dirty", RegNext(resp.valid) && resp.bits.self.dirty)
+  XSPerfAccumulate(cacheParams, "selfdir_TIP", RegNext(resp.valid) && resp.bits.self.state === TIP)
+  XSPerfAccumulate(cacheParams, "selfdir_BRANCH", RegNext(resp.valid) && resp.bits.self.state === BRANCH)
+  XSPerfAccumulate(cacheParams, "selfdir_TRUNK", RegNext(resp.valid) && resp.bits.self.state === TRUNK)
+  XSPerfAccumulate(cacheParams, "selfdir_INVALID", RegNext(resp.valid) && resp.bits.self.state === INVALID)
   //val perfinfo = IO(new Bundle(){
   //  val perfEvents = Output(new PerfEventsBundle(numPCntHcDir))
   //})
   val perfinfo = IO(Output(Vec(numPCntHcDir, (UInt(6.W)))))
   val perfEvents = Seq(
     ("selfdir_A_req     ", req_r.replacerInfo.channel(0) && resp.valid                      ),
-    ("selfdir_A_hit     ", req_r.replacerInfo.channel(0) && resp.valid && resp.bits.self.hit),
+    ("selfdir_A_hit     ", RegNext(req_r.replacerInfo.channel(0) && resp.valid) && resp.bits.self.hit),
     ("selfdir_B_req     ", req_r.replacerInfo.channel(1) && resp.valid                      ),
-    ("selfdir_B_hit     ", req_r.replacerInfo.channel(1) && resp.valid && resp.bits.self.hit),
+    ("selfdir_B_hit     ", RegNext(req_r.replacerInfo.channel(1) && resp.valid) && resp.bits.self.hit),
     ("selfdir_C_req     ", req_r.replacerInfo.channel(2) && resp.valid                      ),
-    ("selfdir_C_hit     ", req_r.replacerInfo.channel(2) && resp.valid && resp.bits.self.hit),
-    ("selfdir_dirty     ", resp.valid && resp.bits.self.dirty                               ),
-    ("selfdir_TIP       ", resp.valid && resp.bits.self.state === TIP                       ),
-    ("selfdir_BRANCH    ", resp.valid && resp.bits.self.state === BRANCH                    ),
-    ("selfdir_TRUNK     ", resp.valid && resp.bits.self.state === TRUNK                     ),
-    ("selfdir_INVALID   ", resp.valid && resp.bits.self.state === INVALID                   ),
+    ("selfdir_C_hit     ", RegNext(req_r.replacerInfo.channel(2) && resp.valid) && resp.bits.self.hit),
+    ("selfdir_dirty     ", RegNext(resp.valid) && resp.bits.self.dirty                               ),
+    ("selfdir_TIP       ", RegNext(resp.valid) && resp.bits.self.state === TIP                       ),
+    ("selfdir_BRANCH    ", RegNext(resp.valid) && resp.bits.self.state === BRANCH                    ),
+    ("selfdir_TRUNK     ", RegNext(resp.valid) && resp.bits.self.state === TRUNK                     ),
+    ("selfdir_INVALID   ", RegNext(resp.valid) && resp.bits.self.state === INVALID                   ),
   )
 
   for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(perfEvents).zipWithIndex) {