Merge branch 'master' of https://github.com/ruiszhang/HuanCun into hi…

…tLevel

.github/workflows/main.yml

@@ -40,7 +40,7 @@ jobs:
       - name: Setup Mill
         uses: jodersky/[email protected]
         with:
-          mill-version: 0.9.8
+          mill-version: 0.11.1
 
       # - name: Check scalafmt
       #   run: make checkformat
@@ -82,7 +82,7 @@ jobs:
       - name: Setup Mill
         uses: jodersky/[email protected]
         with:
-          mill-version: 0.9.8
+          mill-version: 0.11.1
 
       # - name: Check scalafmt
       #   run: make checkformat

.gitignore

@@ -4,3 +4,6 @@ out/
 .idea_modules/
 test_run_dir/
 build/
+.bloop/
+.metals/
+.vscode/

.mill-version

@@ -1 +1 @@
-0.9.8
+0.11.1

Makefile

@@ -1,6 +1,6 @@
 init:
 	git submodule update --init
-	cd rocket-chip && git submodule update --init hardfloat api-config-chipsalliance
+	cd rocket-chip && git submodule update --init hardfloat cde
 
 compile:
 	mill -i HuanCun.compile
@@ -11,26 +11,25 @@ test:
 
 test-top-l2:
 	mill -i HuanCun.test.runMain huancun.TestTop_L2 -td build
-	mv build/TestTop_L2.v build/TestTop.v
 
 test-top-l2standalone:
 	mill -i HuanCun.test.runMain huancun.TestTop_L2_Standalone -td build
-	mv build/TestTop_L2_Standalone.v build/TestTop.v
 
 test-top-l2l3:
 	mill -i HuanCun.test.runMain huancun.TestTop_L2L3 -td build
-	mv build/TestTop_L2L3.v build/TestTop.v
 
 test-top-fullsys:
 	mill -i HuanCun.test.runMain huancun.TestTop_FullSys -td build
-	mv build/TestTop_FullSys.v build/TestTop.v
 
 basic-test:
 	mill -i HuanCun.test.testOnly -o -s huancun.ConnectionTester
 
 bsp:
 	mill -i mill.bsp.BSP/install
 
+idea:
+	mill -i mill.scalalib.GenIdea/idea
+
 clean:
 	rm -rf ./build
 

build.sc

@@ -1,16 +1,16 @@
 import mill._
 import scalalib._
 import scalafmt._
+import $file.common
 import $file.`rocket-chip`.common
-import $file.`rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build
-import $file.`rocket-chip`.hardfloat.build
+import $file.`rocket-chip`.cde.common
+import $file.`rocket-chip`.hardfloat.common
 
 val defaultVersions = Map(
-  "chisel3" -> "3.5.0",
-  "chisel3-plugin" -> "3.5.0",
-  "chiseltest" -> "0.5.2",
-  "scala" -> "2.12.13",
-  "scalatest" -> "3.2.7"
+  "chisel3" -> "3.6.0",
+  "chisel3-plugin" -> "3.6.0",
+  "chiseltest" -> "0.6.2",
+  "scala" -> "2.13.10",
 )
 
 def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = false) = {
@@ -21,98 +21,74 @@ def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = fa
     ivy"$org::$dep:$version"
 }
 
-trait CommonModule extends ScalaModule {
-  override def scalaVersion = defaultVersions("scala")
+trait HasChisel extends ScalaModule {
+  def chiselModule: Option[ScalaModule] = None
 
-  override def scalacOptions = Seq("-Xsource:2.11")
+  def chiselPluginJar: T[Option[PathRef]] = None
 
-  val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
+  def chiselIvy: Option[Dep] = Some(getVersion("chisel3"))
 
-  override def compileIvyDeps = Agg(macroParadise)
-  override def scalacPluginIvyDeps = Agg(macroParadise, getVersion("chisel3-plugin", cross = true))
+  def chiselPluginIvy: Option[Dep] = Some(getVersion("chisel3-plugin", cross=true))
 
-}
+  override def scalaVersion = defaultVersions("scala")
 
-object rocketchip extends `rocket-chip`.common.CommonRocketChip {
+  override def scalacOptions = super.scalacOptions() ++
+    Agg("-language:reflectiveCalls", "-Ymacro-annotations", "-Ytasty-reader")
 
-  val rcPath = os.pwd / "rocket-chip"
+  override def ivyDeps = super.ivyDeps() ++ Agg(chiselIvy.get)
 
-  override def scalaVersion = defaultVersions("scala")
+  override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg(chiselPluginIvy.get)
+}
 
-  override def scalacOptions = Seq("-Xsource:2.11")
+object rocketchip extends `rocket-chip`.common.RocketChipModule with HasChisel {
 
+  val rcPath = os.pwd / "rocket-chip"
   override def millSourcePath = rcPath
 
-  object configRocket extends `rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule {
-    override def millSourcePath = rcPath / "api-config-chipsalliance" / "design" / "craft"
+  def mainargsIvy = ivy"com.lihaoyi::mainargs:0.5.0"
 
-    override def scalaVersion = T {
-      rocketchip.scalaVersion()
-    }
+  def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.5"
 
-    override def pomSettings = T {
-      rocketchip.pomSettings()
-    }
-
-    override def publishVersion = T {
-      rocketchip.publishVersion()
-    }
+  object macros extends `rocket-chip`.common.MacrosModule with HasChisel {
+    def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${scalaVersion}"
   }
 
-  object hardfloatRocket extends `rocket-chip`.hardfloat.build.hardfloat {
-    override def millSourcePath = rcPath / "hardfloat"
-
-    override def scalaVersion = T {
-      rocketchip.scalaVersion()
-    }
-
-    def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
-      common.getVersion("chisel3")
-    ) else Agg.empty[Dep]
-
-    def chisel3PluginIvyDeps = Agg(common.getVersion("chisel3-plugin", cross=true))
+  object cde extends `rocket-chip`.cde.common.CDEModule with HasChisel {
+    override def millSourcePath = rcPath / "cde" / "cde"
   }
 
-  def hardfloatModule = hardfloatRocket
+  object hardfloat extends `rocket-chip`.hardfloat.common.HardfloatModule with HasChisel {
+    override def millSourcePath = rcPath / "hardfloat" / "hardfloat"
+  }
 
-  def configModule = configRocket
+  def macrosModule = macros
 
-}
+  def hardfloatModule = hardfloat
 
+  def cdeModule = cde
 
-object utility extends SbtModule with ScalafmtModule with CommonModule {
+}
 
-  override def ivyDeps = Agg(common.getVersion("chisel3"))
 
+object utility extends SbtModule with HasChisel {
   override def millSourcePath = os.pwd / "Utility"
 
   override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
 }
 
 
-object HuanCun extends SbtModule with ScalafmtModule with CommonModule {
+object HuanCun extends SbtModule with HasChisel with millbuild.common.HuanCunModule {
 
   override def millSourcePath = millOuterCtx.millSourcePath
 
+  def rocketModule: ScalaModule = rocketchip
 
-  override def ivyDeps = super.ivyDeps() ++ Agg(
-    getVersion("chisel3"),
-    getVersion("chiseltest"),
-  )
+  def utilityModule: ScalaModule = utility
 
-  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip, utility)
-
-  object test extends Tests {
+  object test extends SbtModuleTests with TestModule.ScalaTest {
     override def ivyDeps = super.ivyDeps() ++ Agg(
-      getVersion("scalatest","org.scalatest")
+      getVersion("chiseltest"),
     )
-
-    def testFrameworks = Seq("org.scalatest.tools.Framework")
-
-  /*
-    def testOnly(args: String*) = T.command {
-      super.runMain("org.scalatest.tools.Runner", args: _*)
-    }
-  */
   }
+
 }

common.sc

@@ -0,0 +1,12 @@
+import mill._
+import scalalib._
+
+trait HuanCunModule extends ScalaModule {
+
+  def rocketModule: ScalaModule
+
+  def utilityModule: ScalaModule
+
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketModule, utilityModule)
+
+}

src/main/resources/STD_CLKGT_func.v

@@ -10,11 +10,18 @@ module STD_CLKGT_func (
 
   assign clk_en = E | TE;
 
+`ifdef VERILATOR_5
+  always @(CK or clk_en) begin
+    if (CK == 1'b0)
+      clk_en_reg <= clk_en;
+  end
+`else
   always @(posedge CK) 
     begin
       clk_en_reg = clk_en;
     end
+`endif
 
   assign Q = CK & clk_en_reg;
 
-endmodule // Copy from Xihu
+endmodule

src/main/resources/TLLogWriter.v

@@ -31,7 +31,7 @@ module TLLogWriter(
     input clock,
     input reset
 );
-    parameter string prefix;
+    parameter string prefix = "undefined";
 
     always @(posedge clock) begin
         if(wen && !reset) begin

src/main/scala/huancun/BankedXbar.scala

@@ -2,7 +2,7 @@ package huancun
 
 import chisel3._
 import chisel3.util._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.BundleField
@@ -113,8 +113,8 @@ class XbarCircuit
     val out = MixedVec(edgeOut.map(e => TLBundle(e.bundle)))
   })
 
-  val inSeq = io.in.zip(edgeIn)
-  val outSeq = io.out.zip(edgeOut)
+  val inSeq = io.in.zip(edgeIn).toSeq
+  val outSeq = io.out.zip(edgeOut).toSeq
 
   TLXbar.circuit(policy, inSeq, outSeq)
 

src/main/scala/huancun/BaseDirectory.scala

@@ -19,7 +19,7 @@
 
 package huancun
 
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import chisel3.util.random.LFSR
@@ -68,7 +68,7 @@ class SubDirectory[T <: Data](
   dir_hit_fn: T => Bool,
   invalid_way_sel: (Seq[T], UInt) => (Bool, UInt),
   replacement: String)(implicit p: Parameters)
-    extends MultiIOModule {
+    extends Module {
 
   val setBits = log2Ceil(sets)
   val wayBits = log2Ceil(ways)
@@ -132,61 +132,61 @@ class SubDirectory[T <: Data](
   if(eccBits > 0){
     val eccArray = Module(new SRAMTemplate(UInt(eccBits.W), sets, ways, singlePort = true, input_clk_div_by_2 = clk_div_by_2))
     eccArray.io.w(
-      io.tag_w.fire(),
+      io.tag_w.fire,
       tagCode.encode(io.tag_w.bits.tag).head(eccBits),
       io.tag_w.bits.set,
       UIntToOH(io.tag_w.bits.way)
     )
     if (clk_div_by_2) {
       eccArray.clock := masked_clock
     }
-    eccRead := eccArray.io.r(io.read.fire(), io.read.bits.set).resp.data
+    eccRead := eccArray.io.r(io.read.fire, io.read.bits.set).resp.data
   } else {
     eccRead.foreach(_ := 0.U)
   }
 
   tagArray.io.w(
-    io.tag_w.fire(),
+    io.tag_w.fire,
     io.tag_w.bits.tag,
     io.tag_w.bits.set,
     UIntToOH(io.tag_w.bits.way)
   )
-  tagRead := tagArray.io.r(io.read.fire(), io.read.bits.set).resp.data
+  tagRead := tagArray.io.r(io.read.fire, io.read.bits.set).resp.data
 
   if (clk_div_by_2) {
     metaArray.clock := masked_clock
     tagArray.clock := masked_clock
   }
 
-  val reqReg = RegEnable(io.read.bits, enable = io.read.fire())
+  val reqReg = RegEnable(io.read.bits, io.read.fire)
   val reqValidReg = RegInit(false.B)
   if (clk_div_by_2) {
-    reqValidReg := RegNext(io.read.fire())
+    reqValidReg := RegNext(io.read.fire)
   } else {
-    reqValidReg := io.read.fire()
+    reqValidReg := io.read.fire
   }
 
   val hit_s1 = Wire(Bool())
   val way_s1 = Wire(UInt(wayBits.W))
 
   val repl = ReplacementPolicy.fromString(replacement, ways)
   val repl_state = if(replacement == "random"){
-    when(io.tag_w.fire()){
+    when(io.tag_w.fire){
       repl.miss
     }
     0.U
   } else {
     val replacer_sram = Module(new SRAMTemplate(UInt(repl.nBits.W), sets, singlePort = true, shouldReset = true))
-    val repl_sram_r = replacer_sram.io.r(io.read.fire(), io.read.bits.set).resp.data(0)
+    val repl_sram_r = replacer_sram.io.r(io.read.fire, io.read.bits.set).resp.data(0)
     val repl_state_hold = WireInit(0.U(repl.nBits.W))
-    repl_state_hold := HoldUnless(repl_sram_r, RegNext(io.read.fire(), false.B))
+    repl_state_hold := HoldUnless(repl_sram_r, RegNext(io.read.fire, false.B))
     val next_state = repl.get_next_state(repl_state_hold, way_s1)
     replacer_sram.io.w(replacer_wen, RegNext(next_state), RegNext(reqReg.set), 1.U)
     repl_state_hold
   }
 
   io.resp.valid := reqValidReg
-  val metas = metaArray.io.r(io.read.fire(), io.read.bits.set).resp.data
+  val metas = metaArray.io.r(io.read.fire, io.read.bits.set).resp.data
   val tagMatchVec = tagRead.map(_(tagBits - 1, 0) === reqReg.tag)
   val metaValidVec = metas.map(dir_hit_fn)
   val hitVec = tagMatchVec.zip(metaValidVec).map(x => x._1 && x._2)
@@ -200,7 +200,7 @@ class SubDirectory[T <: Data](
      stage 1: generate hit/way, io.resp.valid = TRUE (will latch into MSHR)
      stage 2: output latched hit/way, output dir/tag
   */
-  hit_s1 := Cat(hitVec).orR()
+  hit_s1 := Cat(hitVec).orR
   way_s1 := Mux(reqReg.wayMode, reqReg.way, Mux(hit_s1, hitWay, chosenWay))
 
   val hit_s2 = RegEnable(hit_s1, false.B, reqValidReg)

src/main/scala/huancun/BaseMSHR.scala

@@ -1,6 +1,6 @@
 package huancun
 
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import huancun.prefetch._