prefetch: tp-meta supports hartid-tagged hit comparison (#155)

OpenXiangShan · Oct 26, 2023 · fe18821 · fe18821
1 parent b317d0c
commit fe18821
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Showing 2 changed files with 3 additions and 6 deletions.
diff --git a/src/main/scala/huancun/Common.scala b/src/main/scala/huancun/Common.scala
@@ -244,11 +244,9 @@ class TPmetaReq extends Bundle {
   val way = UInt(8.W)
   val wmode = Bool()
   val rawData = Vec(16, UInt((36-6).W))
-  val mode = UInt(3.W)
 }
 
 class TPmetaResp extends Bundle {
   val hartid = UInt(4.W)
   val rawData = Vec(16, UInt((36-6).W))
-  val mode = UInt(3.W)
 }
diff --git a/src/main/scala/huancun/prefetch/TPmeta.scala b/src/main/scala/huancun/prefetch/TPmeta.scala
@@ -31,7 +31,7 @@ class TPmetaIO(implicit p: Parameters) extends TPmetaBundle {
 
 class metaEntry(implicit p:Parameters) extends TPmetaBundle {
   val rawData = Vec(16, UInt((36-6).W))
-  val mode = UInt(3.W)
+  val hartid = UInt(4.W)
   // TODO: val compressedData = UInt(512.W)
 }
 
@@ -50,7 +50,7 @@ class TPmeta(implicit p: Parameters) extends TPmetaModule
 
   val wdata = Wire(new metaEntry())
   wdata.rawData := io.req.bits.rawData
-  wdata.mode := io.req.bits.mode
+  wdata.hartid := io.req.bits.hartid
   tpDataTable.io.w.apply(
     valid = writeReqValid,
     data = wdata,
@@ -66,9 +66,8 @@ class TPmeta(implicit p: Parameters) extends TPmetaModule
     rdata := tpDataTable.io.r.resp.data(readReqReg.way)
   }
 
-  io.resp.valid := RegNext(readReqValidReg)
+  io.resp.valid := RegNext(readReqValidReg) && (rdata.hartid === RegNext(readReqReg).hartid)
   io.resp.bits.rawData := rdata.rawData
-  io.resp.bits.mode := rdata.mode
   io.resp.bits.hartid := RegNext(readReqReg).hartid
   io.req.ready := true.B
 }