fix(csr, difftest): remove skip csr and add diffevent to csr

Remove skip csr for xip, menvcfg, henvcfg to diff Add diffevent to support no reg interrupt pending
OpenXiangShan · Sep 27, 2024 · 01b0b75 · 01b0b75
1 parent bbaa6b7
commit 01b0b75
Showing 1 changed file with 35 additions and 7 deletions.
diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
@@ -774,12 +774,7 @@ class NewCSR(implicit val p: Parameters) extends Module
     (addr >= CSRs.mcycle.U) && (addr <= CSRs.mhpmcounter31.U) ||
     (addr === mcountinhibit.addr.U) ||
     (addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U) ||
-    (addr === CSRs.mip.U) || (addr === CSRs.sip.U) || (addr === CSRs.vsip.U) ||
-    (addr === CSRs.hip.U) || (addr === CSRs.mvip.U) || (addr === CSRs.hvip.U) ||
-    Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR ||
-    (addr === CSRs.menvcfg.U) ||
-    (addr === CSRs.henvcfg.U) ||
-    (addr === CSRs.stimecmp.U)
+    Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR
   )
 
   // flush
@@ -1288,7 +1283,7 @@ class NewCSR(implicit val p: Parameters) extends Module
     diffCSRState.mcause         := mcause.rdata.asUInt
     diffCSRState.scause         := scause.rdata.asUInt
     diffCSRState.satp           := satp.rdata.asUInt
-    diffCSRState.mip            := mip.regOut.asUInt
+    diffCSRState.mip            := mip.rdata.asUInt
     diffCSRState.mie            := mie.rdata.asUInt
     diffCSRState.mscratch       := mscratch.rdata.asUInt
     diffCSRState.sscratch       := sscratch.rdata.asUInt
@@ -1344,6 +1339,39 @@ class NewCSR(implicit val p: Parameters) extends Module
     diffHCSRState.vsatp       := vsatp.rdata.asUInt
     diffHCSRState.vsscratch   := vsscratch.rdata.asUInt
 
+    val platformIRPMeipChange = !platformIRP.MEIP &&  RegNext(platformIRP.MEIP) ||
+                                 platformIRP.MEIP && !RegNext(platformIRP.MEIP) ||
+                                !fromAIA.meip     &&  RegNext(fromAIA.meip)     ||
+                                 fromAIA.meip     && !RegNext(fromAIA.meip)
+    val platformIRPMtipChange = !platformIRP.MTIP &&  RegNext(platformIRP.MTIP) || platformIRP.MTIP && !RegNext(platformIRP.MTIP)
+    val platformIRPMsipChange = !platformIRP.MSIP &&  RegNext(platformIRP.MSIP) || platformIRP.MSIP && !RegNext(platformIRP.MSIP)
+    val platformIRPSeipChange = !platformIRP.SEIP &&  RegNext(platformIRP.SEIP) ||
+                                 platformIRP.SEIP && !RegNext(platformIRP.SEIP) ||
+                                !fromAIA.seip     &&  RegNext(fromAIA.seip)     ||
+                                 fromAIA.seip     && !RegNext(fromAIA.seip)
+    val platformIRPStipChange = !sstcIRGen.o.STIP &&  RegNext(sstcIRGen.o.STIP) || sstcIRGen.o.STIP && !RegNext(sstcIRGen.o.STIP)
+    val platformIRPVseipChange = !platformIRP.VSEIP &&  RegNext(platformIRP.VSEIP) ||
+                                  platformIRP.VSEIP && !RegNext(platformIRP.VSEIP) ||
+                                 !hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) &&  RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)) ||
+                                  hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) && !RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt))
+    val platformIRPVstipChange = !platformIRP.VSTIP && RegNext(platformIRP.VSTIP) || platformIRP.VSTIP && !RegNext(platformIRP.VSTIP)
+    val lcofiReqChange         = !lcofiReq && RegNext(lcofiReq) || lcofiReq && !RegNext(lcofiReq)
+
+    val diffNonRegInterruptPendingEvent = DifftestModule(new DiffNonRegInterruptPendingEvent)
+    diffNonRegInterruptPendingEvent.coreid           := hartId
+    diffNonRegInterruptPendingEvent.valid            := platformIRPMeipChange || platformIRPMtipChange || platformIRPMsipChange ||
+                                                        platformIRPSeipChange || platformIRPStipChange ||
+                                                        platformIRPVseipChange || platformIRPVstipChange ||
+                                                        lcofiReqChange
+    diffNonRegInterruptPendingEvent.platformIRPMeip  := platformIRP.MEIP || fromAIA.meip
+    diffNonRegInterruptPendingEvent.platformIRPMtip  := platformIRP.MTIP
+    diffNonRegInterruptPendingEvent.platformIRPMsip  := platformIRP.MSIP
+    diffNonRegInterruptPendingEvent.platformIRPSeip  := platformIRP.SEIP || fromAIA.seip
+    diffNonRegInterruptPendingEvent.platformIRPStip  := sstcIRGen.o.STIP
+    diffNonRegInterruptPendingEvent.platformIRPVseip := platformIRP.VSEIP || hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)
+    diffNonRegInterruptPendingEvent.platformIRPVstip := sstcIRGen.o.VSTIP
+    diffNonRegInterruptPendingEvent.localCounterOverflowInterruptReq  := lcofiReq
+
   }
 }