instinfo: set basicDB and remove invalid annotation

OpenXiangShan · Sep 10, 2024 · 65e844f · 65e844f
1 parent 248b9a0
commit 65e844f
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala
@@ -1284,8 +1284,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   if (!env.FPGAPlatform) {
     val instTableName = "InstTable" + p(XSCoreParamsKey).HartId.toString
     val instSiteName = "Rob" + p(XSCoreParamsKey).HartId.toString
-    val debug_instTable = ChiselDB.createTable(instTableName, new InstInfoEntry)
-    // FIXME lyq: only get inst (alu, bj, ls) in exuWriteback
+    val debug_instTable = ChiselDB.createTable(instTableName, new InstInfoEntry, basicDB = true)
     for (wb <- exuWBs) {
       when(wb.valid) {
         val debug_instData = Wire(new InstInfoEntry)