timing(BusyTable, RegCacheTagModule): loadDependency do not need clea…

…r by cancel
OpenXiangShan · Oct 25, 2024 · 67af58f · 67af58f
1 parent e311c27
commit 67af58f
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diff --git a/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala b/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala
@@ -93,7 +93,6 @@ class RegCacheTagModule
     }
     .elsewhen (io.cancelVec(i)) {
       v(i)   := false.B
-      loadDependency(i) := 0.U.asTypeOf(loadDependency(i))
     }
     .elsewhen (loadDependency(i).map(x => x.orR).reduce(_ || _)) {
       loadDependency(i) := loadDependency(i).map(l => l << 1)

diff --git a/src/main/scala/xiangshan/backend/rename/BusyTable.scala b/src/main/scala/xiangshan/backend/rename/BusyTable.scala
@@ -126,9 +126,6 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int, numPhyPregs: Int, pregWB:
     when(wakeUpMask(idx)) {
       ldDp := (if (wakeUpIn.nonEmpty) Mux1H(wakeupOHVec(idx), shiftLoadDependency) else 0.U.asTypeOf(ldDp))
     }
-    .elsewhen(allocMask(idx) || wbMask(idx) || ldCancelMask(idx)) {
-      ldDp := 0.U.asTypeOf(ldDp)
-    }
     .elsewhen(ldDp.map(x => x.orR).reduce(_ | _)) {
       ldDp := VecInit(ldDp.map(x => x << 1))
     }