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feat(IMSIC): combine M/S mode axi4lite ports into single port (#3519)
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Signed-off-by: Jiuyue Ma <[email protected]>
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@forever043
forever043 committed Sep 12, 2024
1 parent b30cb8b commit 9143e23
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Showing 3 changed files with 64 additions and 29 deletions.
71 changes: 52 additions & 19 deletions src/main/scala/device/imsic_axi_top.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,8 @@ class imsic_axi_top(

class imsic_bus_top(
useTL: Boolean = false,
baseAddress: (BigInt, BigInt), /* (M-mode, S/VS-mode) */
maxHarts: Int = 512,
AXI_ID_WIDTH: Int = 5,
AXI_ADDR_WIDTH: Int = 32,
NR_INTP_FILES: Int = 7,
Expand All @@ -78,23 +80,44 @@ class imsic_bus_top(
private val INTP_FILE_WIDTH = log2Ceil(NR_INTP_FILES)
private val MSI_INFO_WIDTH = NR_HARTS_WIDTH + INTP_FILE_WIDTH + NR_SRC_WIDTH

private val tuple_axi4_tl = Option.when(useTL) {
val tlnodes = Seq.fill(2)(TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
"tl",
sourceId = IdRange(0, 1)
))
))))
val axi4nodes = Seq.fill(2)(AXI4SlaveNode(Seq(AXI4SlavePortParameters(
private val m_base = baseAddress._1;
private val m_size = maxHarts * 0x1000;
private val s_base = baseAddress._2;
private val s_size = maxHarts * 0x8000;

println(f"IMSIC: address-mapping for ${maxHarts} HARTs")
println(f"IMSIC: M-mode: [0x${m_base}%08X, 0x${m_base + m_size - 1}%08X]")
println(f"IMSIC: S/VS-mode: [0x${s_base}%08X, 0x${s_base + s_size - 1}%08X]")

private val axi4nodes = Seq(
AXI4SlaveNode(Seq(AXI4SlavePortParameters(
Seq(AXI4SlaveParameters(
Seq(AddressSet(m_base, m_size - 1)),
regionType = RegionType.UNCACHED,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0)
)),
beatBytes = 4
))),
AXI4SlaveNode(Seq(AXI4SlavePortParameters(
Seq(AXI4SlaveParameters(
Seq(AddressSet(0x0, (1L << AXI_ADDR_WIDTH) - 1)),
Seq(AddressSet(s_base, s_size - 1)),
regionType = RegionType.UNCACHED,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0)
)),
beatBytes = 4
))))

val tl = Option.when(useTL) {
val tlnodes = Seq.fill(2)(TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
"tl",
sourceId = IdRange(0, 1)
))
))))
axi4nodes zip tlnodes foreach { case (axi4node, tlnode) =>
axi4node :=
AXI4IdIndexer(AXI_ID_WIDTH) :=
Expand All @@ -107,22 +130,32 @@ class imsic_bus_top(
tlnode
}

(axi4nodes, tlnodes)
tlnodes
}

val axi4 = tuple_axi4_tl.map(_._1)
private val tl = tuple_axi4_tl.map(_._2)
val tl_m = tl.map(x => InModuleBody(x(0).makeIOs()))
val tl_s = tl.map(x => InModuleBody(x(1).makeIOs()))

val axiMasterNode = Option.when(!useTL) {
val node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
Seq(AXI4MasterParameters(
name = "s_axi_",
id = IdRange(0, 1 << AXI_ID_WIDTH)
))
)))
val xbar = AXI4Xbar(TLArbiter.lowestIndexFirst)
axi4nodes.foreach { _ := xbar }
xbar := node
node
}

class imsic_bus_top_imp(wrapper: imsic_bus_top) extends LazyModuleImp(wrapper) {
// imsic csr top io
val o_msi_info = IO(Output(UInt(MSI_INFO_WIDTH.W)))
val o_msi_info_vld = IO(Output(Bool()))

// axi4lite io
val m_s = Option.when(!useTL)(IO(Flipped(new VerilogAXI4LiteRecord(AXI_ADDR_WIDTH, 32, AXI_ID_WIDTH))))
val s_s = Option.when(!useTL)(IO(Flipped(new VerilogAXI4LiteRecord(AXI_ADDR_WIDTH, 32, AXI_ID_WIDTH))))
val axi4lite = Option.when(!useTL)(IO(Flipped(new VerilogAXI4LiteRecord(AXI_ADDR_WIDTH, 32, AXI_ID_WIDTH))))

// imsic axi top
val u_imsic_axi_top = Module(new imsic_axi_top)
Expand All @@ -137,14 +170,14 @@ class imsic_bus_top(
o_msi_info_vld := u_imsic_axi_top.io.o_msi_info_vld

// connection: axi4lite
m_s.foreach(_ <> u_imsic_axi_top.io.m_s)
s_s.foreach(_ <> u_imsic_axi_top.io.s_s)
axi4lite.foreach {
_.viewAs[AXI4LiteBundle].connectToAXI4(wrapper.axiMasterNode.get.out.head._1)
}

// connection: axi4
wrapper.axi4.foreach { axi4 =>
axi4.map(_.in.head._1) zip Seq(u_imsic_axi_top.io.m_s, u_imsic_axi_top.io.s_s) foreach {
wrapper.axi4nodes.map(_.in.head._1) zip
Seq(u_imsic_axi_top.io.m_s, u_imsic_axi_top.io.s_s) foreach {
case (axi4, axi4lite) => axi4lite.viewAs[AXI4LiteBundle].connectFromAXI4(axi4)
}
}
}

Expand Down
11 changes: 6 additions & 5 deletions src/main/scala/top/XSNoCTop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,10 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
})))

// imsic bus top
val u_imsic_bus_top = LazyModule(new imsic_bus_top(soc.IMSICUseTL))
val u_imsic_bus_top = LazyModule(new imsic_bus_top(
useTL = soc.IMSICUseTL,
baseAddress = (0x3A800000, 0x3B000000)
))

// interrupts
val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
Expand Down Expand Up @@ -103,8 +106,7 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
val clintTime = Input(ValidIO(UInt(64.W)))
})
// imsic axi4lite io
val imsic_m_s = wrapper.u_imsic_bus_top.module.m_s.map(x => IO(chiselTypeOf(x)))
val imsic_s_s = wrapper.u_imsic_bus_top.module.s_s.map(x => IO(chiselTypeOf(x)))
val imsic_axi4lite = wrapper.u_imsic_bus_top.module.axi4lite.map(x => IO(chiselTypeOf(x)))
// imsic tl io
val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
Expand All @@ -122,8 +124,7 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
wrapper.u_imsic_bus_top.module.reset := soc_reset_sync

// imsic axi4lite io connection
wrapper.u_imsic_bus_top.module.m_s.foreach(_ <> imsic_m_s.get)
wrapper.u_imsic_bus_top.module.s_s.foreach(_ <> imsic_s_s.get)
wrapper.u_imsic_bus_top.module.axi4lite.foreach(_ <> imsic_axi4lite.get)

// imsic tl io connection
wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
Expand Down
11 changes: 6 additions & 5 deletions src/main/scala/xiangshan/backend/fu/PMA.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -113,9 +113,12 @@ trait PMAMethod extends PMAConst {
MemMap("h00_3802_2000", "h00_3900_0000", "h0", "Reserved", ""),
MemMap("h00_3900_0000", "h00_3900_1FFF", "h0", "L3CacheCtrl", "RW"),
MemMap("h00_3900_2000", "h00_39FF_FFFF", "h0", "Reserved", ""),
MemMap("h00_3A00_0000", "h00_3A00_0FFF", "h0", "PLL0", "RW),
MemMap('h00_3A00_1000", "h00_3BFF_FFFF", "h0", "Reserved", ""),
MemMap("h00_3C00_0000", "h00_3FFF_FFFF", "h0", "PLIC", "RW"),
MemMap("h00_3A00_0000", "h00_3FFF_FFFF", "h0", "", "RW),
Sub("h00_3A00_0000", "h00_3A00_0FFF", "h0", "PLL0", "RW),
Sub('h00_3A00_1000", "h00_3A7F_FFFF", "h0", "Reserved", "RW"),
Sub('h00_3A80_0000", "h00_3AFF_FFFF", "h0", "IMSIC(M)", "RW"),
Sub('h00_3B00_0000", "h00_3BFF_FFFF", "h0", "IMSIC(S/VS)", "RW"),
Sub("h00_3C00_0000", "h00_3FFF_FFFF", "h0", "PLIC", "RW"),
MemMap("h00_4000_0000", "h00_7FFF_FFFF", "h0", "PCIe", "RW"),
MemMap("h00_8000_0000", " MAX_ADDRESS ", "h0", "DDR", "RWXIDSA"),
)
Expand Down Expand Up @@ -155,8 +158,6 @@ trait PMAMethod extends PMAConst {

addPMA(0x0L, range = 0x1000000000000L, c = true, atomic = true, a = 3, x = true, w = true, r = true)
addPMA(0x0L, range = 0x80000000L, a = 3, w = true, r = true)
addPMA(0x3C000000L, a = 1)
addPMA(0x3A001000L, a = 1, w = true, r = true)
addPMA(0x3A000000L, a = 1)
addPMA(0x39002000L, a = 1, w = true, r = true)
addPMA(0x39000000L, a = 1)
Expand Down

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