fix(CSR): Add legalization code for mstatus.MPP, mnstatus.MNPP and dc…

…sr.PRV (#3577)

src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala

@@ -257,6 +257,8 @@ object CSRDefines {
     val U = Value(0.U)
     val S = Value(1.U)
     val M = Value(3.U)
+
+    override def isLegal(enumeration: CSREnumType): Bool = enumeration.isOneOf(U, S, M)
   }
 
   object VirtMode extends CSREnum with RWApply {

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala

@@ -54,7 +54,16 @@ trait EventUpdatePrivStateOutput {
 }
 
 trait EventOutputBase {
-  def getBundleByName(name: String): Valid[CSRBundle]
+  import scala.reflect.runtime.{universe => ru}
+
+  def getBundleByName(name: String): Valid[CSRBundle] = {
+    val mirror: ru.Mirror = ru.runtimeMirror(getClass.getClassLoader)
+    val im = mirror.reflect(this)
+    val classSymbol: ru.ClassSymbol = im.symbol.asClass
+    val fieldSymbol = classSymbol.info.decl(ru.TermName(name)).asTerm
+    val fieldMirror: ru.FieldMirror = mirror.reflect(this).reflectField(fieldSymbol)
+    fieldMirror.get.asInstanceOf[Valid[CSRBundle]]
+  }
 }
 
 trait CSREventBase {
@@ -140,6 +149,16 @@ class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSP
   val hvictlIID = Input(UInt(HIIDWidth.W))
 }
 
+trait EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
+  protected def addUpdateBundleInCSREnumType(updateBundle: ValidIO[CSRBundle]): Unit = {
+    (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
+      if (updateBundle.bits.eventFields.contains(source)) {
+        sink.addOtherUpdate(updateBundle.valid, source)
+      }
+    }
+  }
+}
+
 class TargetPCBundle extends Bundle {
   val pc = UInt(XLEN.W)
   val raiseIPF = Bool()

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala

@@ -15,13 +15,6 @@ class DretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventO
   val debugMode = ValidIO(Bool())
   val debugIntrEnable = ValidIO(Bool())
   val targetPc = ValidIO(new TargetPCBundle)
-
-  override def getBundleByName(name: String): ValidIO[CSRBundle] = {
-    name match {
-      case "dcsr" => this.dcsr
-      case "mstatus" => this.mstatus
-    }
-  }
 }
 
 class DretEventInput extends Bundle {
@@ -74,16 +67,10 @@ class DretEventModule(implicit p: Parameters) extends Module with CSREventBase {
   out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.dpc.asUInt)
 }
 
-trait DretEventSinkBundle { self: CSRModule[_] =>
+trait DretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val retFromD = IO(Flipped(new DretEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = retFromD.getBundleByName(self.modName.toLowerCase())
+  addUpdateBundleInCSREnumType(retFromD.getBundleByName(self.modName.toLowerCase()))
 
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case(sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala

@@ -17,13 +17,6 @@ class MNretEventOutput extends Bundle with EventUpdatePrivStateOutput with Event
   val mnstatus  = ValidIO((new MnstatusBundle).addInEvent(_.MNPP, _.MNPV, _.NMIE))
   val mstatus   = ValidIO((new MstatusBundle).addInEvent(_.MPRV))
   val targetPc  = ValidIO(new TargetPCBundle)
-
-  override def getBundleByName(name: String): ValidIO[CSRBundle] = {
-    name match {
-      case "mnstatus"  => this.mnstatus
-      case "mstatus"   => this.mstatus
-    }
-  }
 }
 
 class MNretEventInput extends Bundle {
@@ -74,17 +67,10 @@ class MNretEventModule(implicit p: Parameters) extends Module with CSREventBase
   out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.mnepc.asUInt)
 }
 
-trait MNretEventSinkBundle { self: CSRModule[_] =>
+trait MNretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val retFromMN = IO(Flipped(new MNretEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = retFromMN.getBundleByName(self.modName.toLowerCase())
-
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  addUpdateBundleInCSREnumType(retFromMN.getBundleByName(self.modName.toLowerCase()))
 
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala

@@ -17,13 +17,6 @@ class MretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventO
   val mstatus  = ValidIO((new MstatusBundle).addInEvent(_.MPP, _.MPV, _.MIE, _.MPIE, _.MPRV))
   val tcontrol = ValidIO((new TcontrolBundle).addInEvent(_.MTE))
   val targetPc = ValidIO(new TargetPCBundle)
-
-  override def getBundleByName(name: String): ValidIO[CSRBundle] = {
-    name match {
-      case "mstatus"  => this.mstatus
-      case "tcontrol" => this.tcontrol
-    }
-  }
 }
 
 class MretEventInput extends Bundle {
@@ -77,17 +70,10 @@ class MretEventModule(implicit p: Parameters) extends Module with CSREventBase {
   out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.mepc.asUInt)
 }
 
-trait MretEventSinkBundle { self: CSRModule[_] =>
+trait MretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val retFromM = IO(Flipped(new MretEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = retFromM.getBundleByName(self.modName.toLowerCase())
-
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  addUpdateBundleInCSREnumType(retFromM.getBundleByName(self.modName.toLowerCase()))
 
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala

@@ -19,14 +19,6 @@ class SretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventO
   val hstatus = ValidIO((new HstatusBundle).addInEvent(_.SPV))
   val vsstatus = ValidIO((new SstatusBundle).addInEvent(_.SIE, _.SPIE, _.SPP))
   val targetPc = ValidIO(new TargetPCBundle)
-
-  override def getBundleByName(name: String): ValidIO[CSRBundle] = {
-    name match {
-      case "mstatus" => this.mstatus
-      case "hstatus" => this.hstatus
-      case "vsstatus" => this.vsstatus
-    }
-  }
 }
 
 class SretEventInput extends Bundle {
@@ -111,16 +103,10 @@ class SretEventModule(implicit p: Parameters) extends Module with CSREventBase {
   dontTouch(sretInVS)
 }
 
-trait SretEventSinkBundle { self: CSRModule[_] =>
+trait SretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val retFromS = IO(Flipped(new SretEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = retFromS.getBundleByName(self.modName.toLowerCase())
+  addUpdateBundleInCSREnumType(retFromS.getBundleByName(self.modName.toLowerCase()))
 
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala

@@ -19,13 +19,6 @@ class TrapEntryDEventOutput extends Bundle with EventUpdatePrivStateOutput with
   val targetPc        = ValidIO(new TargetPCBundle)
   val debugMode       = ValidIO(Bool())
   val debugIntrEnable = ValidIO(Bool())
-
-  def getBundleByName(name: String): Valid[CSRBundle] = {
-    name match {
-      case "dcsr" => this.dcsr
-      case "dpc"  => this.dpc
-    }
-  }
 }
 
 class TrapEntryDEventInput(implicit override val p: Parameters) extends TrapEntryEventInput{
@@ -104,16 +97,10 @@ class TrapEntryDEventModule(implicit val p: Parameters) extends Module with CSRE
 
 }
 
-trait TrapEntryDEventSinkBundle { self: CSRModule[_] =>
+trait TrapEntryDEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val trapToD = IO(Flipped(new TrapEntryDEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = trapToD.getBundleByName(self.modName.toLowerCase())
+  addUpdateBundleInCSREnumType(trapToD.getBundleByName(self.modName.toLowerCase()))
 
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala

@@ -23,18 +23,6 @@ class TrapEntryHSEventOutput extends Bundle with EventUpdatePrivStateOutput with
   val htval   = ValidIO((new OneFieldBundle).addInEvent(_.ALL))
   val htinst  = ValidIO((new OneFieldBundle).addInEvent(_.ALL))
   val targetPc  = ValidIO(new TargetPCBundle)
-
-  def getBundleByName(name: String): Valid[CSRBundle] = {
-    name match {
-      case "mstatus" => this.mstatus
-      case "hstatus" => this.hstatus
-      case "sepc"    => this.sepc
-      case "scause"  => this.scause
-      case "stval"   => this.stval
-      case "htval"   => this.htval
-      case "htinst"  => this.htinst
-    }
-  }
 }
 
 class TrapEntryHSEventModule(implicit val p: Parameters) extends Module with CSREventBase {
@@ -154,16 +142,10 @@ class TrapEntryHSEventModule(implicit val p: Parameters) extends Module with CSR
   dontTouch(tvalFillGVA)
 }
 
-trait TrapEntryHSEventSinkBundle { self: CSRModule[_] =>
+trait TrapEntryHSEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val trapToHS = IO(Flipped(new TrapEntryHSEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = trapToHS.getBundleByName(self.modName.toLowerCase())
+  addUpdateBundleInCSREnumType(trapToHS.getBundleByName(self.modName.toLowerCase()))
 
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala

@@ -21,18 +21,6 @@ class TrapEntryMEventOutput extends Bundle with EventUpdatePrivStateOutput with
   val mtinst    = ValidIO((new OneFieldBundle).addInEvent(_.ALL))
   val tcontrol  = ValidIO((new TcontrolBundle).addInEvent(_.MPTE, _.MTE))
   val targetPc  = ValidIO(new TargetPCBundle)
-
-  def getBundleByName(name: String): Valid[CSRBundle] = {
-    name match {
-      case "mstatus"  => this.mstatus
-      case "mepc"     => this.mepc
-      case "mcause"   => this.mcause
-      case "mtval"    => this.mtval
-      case "mtval2"   => this.mtval2
-      case "mtinst"   => this.mtinst
-      case "tcontrol" => this.tcontrol
-    }
-  }
 }
 
 class TrapEntryMEventModule(implicit val p: Parameters) extends Module with CSREventBase {
@@ -142,16 +130,10 @@ class TrapEntryMEventModule(implicit val p: Parameters) extends Module with CSRE
   dontTouch(tvalFillGVA)
 }
 
-trait TrapEntryMEventSinkBundle { self: CSRModule[_] =>
+trait TrapEntryMEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val trapToM = IO(Flipped(new TrapEntryMEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = trapToM.getBundleByName(self.modName.toLowerCase())
+  addUpdateBundleInCSREnumType(trapToM.getBundleByName(self.modName.toLowerCase()))
 
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala

@@ -15,14 +15,6 @@ class TrapEntryMNEventOutput extends Bundle with EventUpdatePrivStateOutput with
   val mnepc    = ValidIO((new Epc           ).addInEvent(_.epc))
   val mncause  = ValidIO((new CauseBundle   ).addInEvent(_.Interrupt, _.ExceptionCode))
   val targetPc = ValidIO(new TargetPCBundle)
-
-  def getBundleByName(name: String): Valid[CSRBundle] = {
-    name match {
-      case "mnstatus"  => this.mnstatus
-      case "mnepc"     => this.mnepc
-      case "mncause"   => this.mncause
-    }
-  }
 }
 
 class TrapEntryMNEventModule(implicit val p: Parameters) extends Module with CSREventBase {
@@ -69,16 +61,10 @@ class TrapEntryMNEventModule(implicit val p: Parameters) extends Module with CSR
 
 }
 
-trait TrapEntryMNEventSinkBundle { self: CSRModule[_] =>
+trait TrapEntryMNEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val trapToMN = IO(Flipped(new TrapEntryMNEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = trapToMN.getBundleByName(self.modName.toLowerCase())
+  addUpdateBundleInCSREnumType(trapToMN.getBundleByName(self.modName.toLowerCase()))
 
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  reconnectReg()
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala

@@ -19,15 +19,6 @@ class TrapEntryVSEventOutput extends Bundle with EventUpdatePrivStateOutput with
   val vscause  = ValidIO((new CauseBundle   ).addInEvent(_.Interrupt, _.ExceptionCode))
   val vstval   = ValidIO((new OneFieldBundle).addInEvent(_.ALL))
   val targetPc = ValidIO(new TargetPCBundle)
-
-  def getBundleByName(name: String): Valid[CSRBundle] = {
-    name match {
-      case "vsstatus" => this.vsstatus
-      case "vsepc"    => this.vsepc
-      case "vscause"  => this.vscause
-      case "vstval"   => this.vstval
-    }
-  }
 }
 
 class TrapEntryVSEventModule(implicit val p: Parameters) extends Module with CSREventBase {
@@ -142,16 +133,10 @@ class TrapEntryVSEventModule(implicit val p: Parameters) extends Module with CSR
   dontTouch(tvalFillGVA)
 }
 
-trait TrapEntryVSEventSinkBundle { self: CSRModule[_] =>
+trait TrapEntryVSEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
   val trapToVS = IO(Flipped(new TrapEntryVSEventOutput))
 
-  private val updateBundle: ValidIO[CSRBundle] = trapToVS.getBundleByName(self.modName.toLowerCase())
+  addUpdateBundleInCSREnumType(trapToVS.getBundleByName(self.modName.toLowerCase()))
 
-  (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
-    if (updateBundle.bits.eventFields.contains(source)) {
-      when(updateBundle.valid) {
-        sink := source
-      }
-    }
-  }
+  reconnectReg()
 }