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When FS is 0 and a fld/fsd specific instruction causes an exception, there is a problem with the value of the mtval register #3864
Comments
Thank you for your issue. |
Thank you for your prompt reply and explanation. Do I need to submit an issue in the xiangshan repository to explain this issue? |
I don’t think it’s necessary to submit another issue. We will fix this problem soon. |
Thank you very much for your prompt reply and for addressing this issue!😄 |
I'll transfer this to OpenXiangShan/XiangShan as this seems not a NEMU bug, and by doing so we can link this to a Pull Request. |
* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs is off Fix #3864 Update: OpenXiangShan/rocket-chip#20 is merged and this PR is rebased, ready to review. --------- Co-authored-by: sinceforYy <[email protected]>
Describe the bug
When the FS field in the mstatus register is 0, executing the
fld fa0, 288 (sp)
instruction causes an illegal instruction exception, and the values of the xiangshan and nemumtval
registers are inconsistent.Specifically, the value of the
xiangshan
mtval register is the machine code of the fld fa0, 288 (sp) instruction.The value of the mtval register in nemu is
0x00003512
To Reproduce
Error log or Screenshots
When I use spike for debugging, the instruction corresponding to
0x00003512
isc.fldsp fa0, 288 (sp)
. After testing, thefsd
command also has this situationNecessary information on versions
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