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When FS is 0 and a fld/fsd specific instruction causes an exception, there is a problem with the value of the mtval register #3864

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fly-1011 opened this issue Nov 8, 2024 · 5 comments · Fixed by #3859

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@fly-1011
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fly-1011 commented Nov 8, 2024

Describe the bug

When the FS field in the mstatus register is 0, executing the fld fa0, 288 (sp) instruction causes an illegal instruction exception, and the values ​​of the xiangshan and nemu mtval registers are inconsistent.

Specifically, the value of the xiangshan mtval register is the machine code of the fld fa0, 288 (sp) instruction.
The value of the mtval register in nemu is 0x00003512

To Reproduce

.section .text
.globl _start
_start:
    li     t0, 0x8000000a00100a00     #FS: 00
    csrw    mstatus, t0 
    fld     fa0, 288(sp)

Error log or Screenshots

image
image

When I use spike for debugging, the instruction corresponding to 0x00003512 is c.fldsp fa0, 288 (sp). After testing, the fsd command also has this situation

image

Necessary information on versions

  • NEMU version: 34ba2259558ed89f5a042179ef0a9131e53ce037 (HEAD, origin/master, origin/HEAD)
@NewPaulWalker
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Thank you for your issue.
This is actually a bug in XiangShan.
The instruction fld fa0, 288(sp) was compiled into a compressed instruction 0x3512 under the C extension.
In XiangShan, the frontend decoding process expands the 16-bit C extension compressed instruction into a 32-bit instruction.
After that, it detects that FS is set to 0, so it stores the expanded instruction in mtval, rather than the original instruction itself.
This issue is currently being fixed by @sinceforYy

@fly-1011
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fly-1011 commented Nov 8, 2024

Thank you for your issue. This is actually a bug in XiangShan. The instruction fld fa0, 288(sp) was compiled into a compressed instruction 0x3512 under the C extension. In XiangShan, the frontend decoding process expands the 16-bit C extension compressed instruction into a 32-bit instruction. After that, it detects that FS is set to 0, so it stores the expanded instruction in mtval, rather than the original instruction itself. This issue is currently being fixed by @sinceforYy

Thank you for your prompt reply and explanation. Do I need to submit an issue in the xiangshan repository to explain this issue?

@NewPaulWalker
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Do I need to submit an issue in the xiangshan repository to explain this issue?

I don’t think it’s necessary to submit another issue. We will fix this problem soon.

@fly-1011
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fly-1011 commented Nov 8, 2024

Do I need to submit an issue in the xiangshan repository to explain this issue?

I don’t think it’s necessary to submit another issue. We will fix this problem soon.

Thank you very much for your prompt reply and for addressing this issue!😄

@ngc7331
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ngc7331 commented Nov 12, 2024

Do I need to submit an issue in the xiangshan repository to explain this issue?

I don’t think it’s necessary to submit another issue. We will fix this problem soon.

I'll transfer this to OpenXiangShan/XiangShan as this seems not a NEMU bug, and by doing so we can link this to a Pull Request.

@ngc7331 ngc7331 transferred this issue from OpenXiangShan/NEMU Nov 12, 2024
Gao-Zeyu pushed a commit that referenced this issue Nov 14, 2024
* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: OpenXiangShan/rocket-chip#20 is merged
and this PR is rebased, ready to review.

---------

Co-authored-by: sinceforYy <[email protected]>
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3 participants