feat(HPM): enable HPMs in CoupledL2 and print them

src/main/scala/xiangshan/L2Top.scala

@@ -166,6 +166,7 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
       val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
       val l2_pmp_resp = Flipped(new PMPRespBundle)
       val l2_hint = ValidIO(new L2ToL1Hint())
+      val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
       // val reset_core = IO(Output(Reset()))
     })
 
@@ -203,6 +204,15 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
       io.l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill
       io.l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate
       io.l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill
+      io.perfEvents := l2.io_perf
+
+      val allPerfEvents = l2.getPerfEvents
+      if (printEventCoding) {
+        for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
+          println("L2 Cache perfEvents Set", name, inc, i)
+        }
+      }
+
       l2.io.l2_tlb_req.resp.valid := io.l2_tlb_req.resp.valid
       l2.io.l2_tlb_req.req.ready := io.l2_tlb_req.req.ready
       l2.io.l2_tlb_req.resp.bits.paddr.head := io.l2_tlb_req.resp.bits.paddr.head
@@ -231,6 +241,7 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
       io.l2_tlb_req.req.bits := DontCare
       io.l2_tlb_req.req_kill := DontCare
       io.l2_tlb_req.resp.ready := true.B
+      io.perfEvents := DontCare
     }
   }
 

src/main/scala/xiangshan/Parameters.scala

@@ -860,7 +860,7 @@ trait HasXSParameter {
   def LFSTEnable = true
 
   def PCntIncrStep: Int = 6
-  def numPCntHc: Int = 25
+  def numPCntHc: Int = 12
   def numPCntPtw: Int = 19
 
   def numCSRPCntFrontend = 8

src/main/scala/xiangshan/XSCore.scala

@@ -84,7 +84,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
     val cpu_halt = Output(Bool())
     val resetInFrontend = Output(Bool())
     val l2_pf_enable = Output(Bool())
-    val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent))
+    val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
     val beu_errors = Output(new XSL1BusErrors())
     val l2_hint = Input(Valid(new L2ToL1Hint()))
     val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2))

src/main/scala/xiangshan/XSTile.scala

@@ -139,8 +139,6 @@ class XSTile()(implicit p: Parameters) extends LazyModule
     l2top.module.io.hartIsInReset.resetInFrontend := core.module.io.resetInFrontend
     io.hartIsInReset := l2top.module.io.hartIsInReset.toTile
 
-    core.module.io.perfEvents <> DontCare
-
     l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache
     l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache
     if (enableL2) {
@@ -157,6 +155,8 @@ class XSTile()(implicit p: Parameters) extends LazyModule
       l2top.module.io.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit
       l2top.module.io.l2_pmp_resp := core.module.io.l2_pmp_resp
       core.module.io.l2_tlb_req <> l2top.module.io.l2_tlb_req
+
+      core.module.io.perfEvents <> l2top.module.io.perfEvents
     } else {
 
       l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2)
@@ -171,6 +171,8 @@ class XSTile()(implicit p: Parameters) extends LazyModule
       core.module.io.l2_tlb_req.req.bits := DontCare
       core.module.io.l2_tlb_req.req_kill := DontCare
       core.module.io.l2_tlb_req.resp.ready := true.B
+
+      core.module.io.perfEvents <> DontCare
     }
 
     io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -59,7 +59,7 @@ class PerfCounterIO(implicit p: Parameters) extends XSBundle {
   val perfEventsFrontend  = Vec(numCSRPCntFrontend, new PerfEvent)
   val perfEventsBackend   = Vec(numCSRPCntCtrl, new PerfEvent)
   val perfEventsLsu       = Vec(numCSRPCntLsu, new PerfEvent)
-  val perfEventsHc        = Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)
+  val perfEventsHc        = Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)
   val retiredInstr = UInt(7.W)
   val frontendInfo = new Bundle {
     val ibufFull  = Bool()