Update README.md (#502)

README.md

@@ -2,7 +2,31 @@
 
 DiffTest (差分测试): a modern co-simulation framework for RISC-V processors.
 
-## Example: Generate Verilog
+## Usage
+
+DiffTest supports the following run-time command-line arguments.
+This list is not complete as we are still working on improving the documentation.
+
+- `-i, --image=FILE` for the workload to be executed by the design-under-test (DUT)
+
+  - DiffTest supports linear (binary, gz, zstd, ELF) and footprint input formats, controlled by build-time and run-time arguments.
+
+  - By default, the image is loaded as a binary file with a linear (continuous) address space starting at 0x8000_0000.
+    This behavior is overrided if an advanced image format (gz, zstd, ELF) is detected.
+
+  - Compressed binary files in gz or zstd formats are supported, determined by leading magic numbers of the image file.
+    Once detected, they will be first decompressed and then loaded into the linear memory.
+    Use `IMAGE_GZ_COMPRESS=0` or `NO_ZSTD_COMPRESSION=1` to disable their support at build-time.
+
+  - ELF files are supported, determined by leading magic numbers of the image file. Use `IMAGE_ELF=0` to disable it at build-time.
+
+  - [Footprint inputs](https://doi.org/10.1145/3649329.3655911) are supported by the run-time argument `--as-footprints`.
+    Basically, every time when a new address is accessed by the CPU, a new data block is read from the image file and put at the accessed address.
+
+For more details on compile-time arguments, see the Makefiles.
+For more details and a full list of supported run-time command-line arguments, run `emu --help`.
+
+## Example: Generate Verilog for DiffTest Interfaces
 
 DiffTest interfaces are provided in [Chisel bundles](src/main/scala/Bundles.scala) and expected to be integrated
 into Chisel designs with auto-generated C++ interfaces.
@@ -20,7 +44,10 @@ After running the following command, files will be generated at `build`.
 make
 ```
 
-## Example Chisel Usage
+We support the DiffTest Profile as a configuration file for DiffTest to record and reconstruct DiffTest interfaces
+through a `json` file.
+
+## Example Chisel Usage: Connecting Your Own Design with DiffTest
 
 We are supporting Chisel 3.6.1 (the last version supporting Scala FIRRTL Compiler)
 as well as 6.5.0 (the latest stable version supporting MLIR FIRRTL Compiler).
@@ -110,7 +137,7 @@ We provide example designs, including:
 
 If you encountered any issues when integrating DiffTest to your own design, feel free to let us know with necessary information on how you have modified your design. We will try our best to assist you.
 
-## APIs
+## APIs (DiffTest Interfaces)
 
 Currently we are supporting the RISC-V base ISA as well as some extensions,
 including Float/Double, Debug, and Vector. We also support checking the cache
@@ -179,8 +206,6 @@ Please set the correct parameters for the interfaces.
 
 There are several plugins to improve the RTL-simulation and debugging process.
 
-See the Makefiles for the compilation time arguments. Run `emu --help` to see the full list of supported run-time arguments.
-
 ### LightSSS: a lightweight simulation snapshot mechanism
 
 After the simulation aborts, we require some debugging information to assist locating the root cause, such as waveform and DUT/REF logs.