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Issues: RTimothyEdwards/netgen
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netgen doesn't handle attributes correctly or escapes inside escapes.
#82
opened Sep 4, 2023 by
d-m-bailey
Verilog ports shorted with assign statements in subcells are not handled correctly.
#81
opened Sep 1, 2023 by
d-m-bailey
Netlists created with ext2spice short resistor should be equivalent to those created without
#80
opened Aug 18, 2023 by
d-m-bailey
parallel/series reduction of resistor network yields size errors.
#76
opened May 20, 2023 by
d-m-bailey
Altering port lists with duplicate ports causes incorrect connectivity
#73
opened Apr 11, 2023 by
d-m-bailey
Looks like python/lvs_manager.py may have been unintentionally added to the repo.
#44
opened Dec 30, 2021 by
d-m-bailey
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