Interim Correlator Register Descriptions

This document will describe the registers and memory blocks used to control the sma_corr bitcode.

1. Sync control
2. Source control
3. Coarse delay interface
4. Walshing interface

Synchronous Signal Control

There are a few signals in sma_corr used for synchronization within the design and across boards. Two of these are armed to externally provided LVDS signals, the so-called Start Of Walsh Frame (SOWF) and the 1 Pulse Per Second (1PPS). The Master CouNTer (MCNT) is used in the networked corner turner for reordering received packets. The period of the SOWF signal is 64 heartbeats or 2^25 / 52 MHz.

sync_ctrl

Signals are armed by the rising edge of the appropriate bit. The ADC sync. source bit tells the fabric which ZDOK to grab its external heartbeat from (used to arm the SOWF), the other input is then assumed to be 1PPS; this bit should normally be set to 0 unless the signals need to be wired differently.

bits	31	30	29	28-1	0
encode	arm SOWF	arm 1PPS	arm MCNT		ADC sync source

Source Control

The sma_corr design has three built-in digital test sources per input (for a total of six) in addition to the external analog ADC sources:

1. a Gaussian white noise generator,
2. a variable sine wave generator, and
3. a combination of 1. and 2.

The noise generators can be seeded independently to provide for fully-, slightly-, or un-correlated signals for debugging correlator logic. The tone generator has an adjustable frequency with 12-bit resolution. Currently, option 3. only supports a combination of the noise with 1/4 the tone, but a variable tone strength may be a feature in the future.

source_ctrl

Each noise source must be given a seed and then armed using a rising edge on the appropriate bit. This causes the generators to start on the next sync pulse (the next internal SOWF) and should be used to synchronize the generators across boards (otherwise they can't be correlated). This register also controls which source is used on which input using the input select bits. These values should be set to one of the following:

0. constant 0
1. constant 1
2. analog ADC input
3. digital noise source
4. sine wave
5. noise-dithered tone

The tone frequency can be set per input with 12-bit accuracy and ranges from 0 to half the sample rate. Note: using source mode 5 (dithered tone) is presently not recommended as it appears the tone overpowers the noise and causes overflows in the F-engine.

bits	31	30	29-18	17-6	5-3	2-0
encode	arm noise 1	arm noise 0	tone freq. 1	tone freq. 0	input sel. 1	input sel. 0

source_seed_1

source_seed_0

The CASPER block used for the digital noise generators provides two outputs and takes a single 32-bit seed. Since our demux factor is 16 (before the F-engine) we need 8 of these blocks. To simplify seeding of the data we use 4-bit seeds which are then expanded to 32-bits internally by appending different non-zero values to the given seed nibbles. These different seeds can be used to adjust the "correlated" component between inputs for a mininum correlation of 1/8 or -9 dB.

bits	31-28	27-24	23-20	19-16	15-12	11-8	7-4	3-0
encode	seed 7	seed 6	seed 5	seed 4	seed 3	seed 2	seed 1	seed 0

Coarse Delay Interface

Coarse delay is applied on a per input basis using a FIFO that is 2^15 samples long. There are two such FIFOs and each must be enabled separately and given a requested depth. Note: there is some pipeline latency associated with the FIFOs but it is the same for both. So if only one is enabled and both delays are set to 0 there will still be a relative latency. Generally both FIFOs should be enable even if only one has non-zero delay.

cdelay_ctrl

bits	31	30	29-15	14-0
encode	enable1	enable0	delay1 (samples)	delay0 (samples)

Walshing Interface

De-Walshing is synchronous to the internally generated heartbeat, every 2^19 / 52 MHz seconds or 88 * 2^15 clock samples of sma_corr. Since the ASIAA ADC supports a single input at 5 GSps each of our ROACH2 F-engines process two inputs max; and as a result only needs to store two Walsh patterns. Simplifying this further is the fact that our back-end will support either 2 GHz dual polarization or 4 GHz single-polarization, i.e. both modes are still a single antenna and thus a single Walsh pattern. Nevertheless, it may be useful during debugging to support two patterns.

walsh_ctrl

bits	31	30	29	28	27-10	9	8	7	6	5	4	3	2	1	0
encode	enable1		enable0			Walsh mask

walsh_status

bits	31-10	9	8	7	6	5	4	3	2	1	0
encode		current Walsh step

walsh_table

The Walsh table block memory stores the LO-applied Walsh phases for every step of the Walsh cycle, the length of which depends on various factors. The Walsh table allows for a maximum of 1024 Walsh steps but the Walsh mask (bits 9-0 of the walsh_ctrl register) controls how deep the fabric will cycle through the Walsh table. The Walsh mask should always be set to 2^W-1 where 2^W is the (power-of-two) requested Walsh table size. General this should be set to 1023 but make sure to provide 1024 steps in the Walsh table, repeating a shorter pattern if necessary.

Each row encodes a single Walsh step using a 4 bit nibble (see the table below), the two least significant bits are the Walsh phase while the two most significant bits are reserved for possible future use. All phases are assumed to be positively applied at the LO and will be de-Walshed in opposite sign. Each input n corresponds to nibble n of the 32-bit word, i.e. bits n * 4 to bits (n + 1) * 4 - 1. Of course, as mentioned above, we only support two inputs which will use the same Walsh pattern so in practice when writing to the table input0 and input1 should have identical values.

bits	31-8	7	6	5	4	3	2	1	0
row0		input1 [0]				input0 [0]
		rsvd		phase		rsvd		phase
...	...	...				...
row1023		input1 [1023]				input0 [1023]
		rsvd		phase		rsvd		phase