Merge pull request #217 from TG9541/stm8l-1

fixes #216: STM8L051F3 USART TX:PA2/RX:PA3 as the default
TG9541 · May 27, 2018 · 138a8ec · 138a8ec
2 parents a866f48 + b6eacb9
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diff --git a/STM8L051F3/README.md b/STM8L051F3/README.md
@@ -0,0 +1,22 @@
+#STM8L051F3P6 Base Image
+
+By default, the USART interface for the STM8L051F3 is configured to support the LSE clock feature (which requires a 32768Hz crystal to be connected to PC5/PC6).
+
+![stm8l051f3p6_](https://user-images.githubusercontent.com/5466977/40583511-8462f470-6190-11e8-8674-84338a991f58.png)
+
+Should a different USART setting be required the configuration can be changed in `boardcore.inc`, or in start-up Forth code, e.g.:
+
+```
+\res MCU: STM8L051
+\res export SYSCFG_RMPCR1 PA_DDR PA_CR1 PC_DDR PC_CR1
+#require ]B!
+#require ]C!
+
+: init ( -- )  \  assign STM8L051 USART to PC5:TX, PC6:RX
+   [ 0 PA_DDR 2 ]B!
+   [ 0 PA_CR1 2 ]B!
+   [ 1 PC_DDR 5 ]B!
+   [ 1 PC_CR1 5 ]B!
+   [ $0C SYSCFG_RMPCR1 ]C!
+   ;
+```
diff --git a/STM8L051F3/boardcore.inc b/STM8L051F3/boardcore.inc
@@ -84,10 +84,9 @@ BKEYCHAR:
 ;       Init board GPIO (except COM ports)
 
 BOARDINIT:
-        ; Board I/O initialization
+        ; Board I/O initialization: enable USART TX->PA2, RX->PA3
         MOV     CLK_PCKENR1,#0x21
-        BSET    PC_DDR,#5
-        BSET    PC_CR1,#5
+        BSET    PA_DDR,#2
+        BSET    PA_CR1,#2
+        MOV     SYSCFG_RMPCR1,#0x1C
         RET
-
-