rsz: Add command for eliminating dead logic

[povik]

Removes instances which are all:

• standard logic cells
• not marked dont touch, not connected to a net marked dont touch
• not in the transitive input cone of a top-level port, or a dont touch cell, dont touch net, or a cell which is not a standard logic cell

In ORFS on nangate45/black_parrot, which has hierarchical synthesis enabled, this finds plenty of cells to eliminate.

At floorplan stage, pre-elimination

Cell type report:                       Count       Area
  Macro                                    24  328372.48
  Tap cell                               9417    2504.92
  Timing Repair Buffer                  26827   39861.70
  Inverter                              33586   19516.42
  Sequential cell                       38477  174264.85
  Multi-Input combinational cell       200734  208349.55
  Total                                309065  772869.92

post-elimination

Removed 40566 instances
Cell type report:                       Count       Area
  Macro                                    24  328372.48
  Tap cell                               9417    2504.92
  Timing Repair Buffer                  24933   36703.21
  Inverter                              30144   17674.37
  Sequential cell                       34168  154779.55
  Multi-Input combinational cell       169813  177765.94
  Total                                268499  717800.47

[github-actions]

clang-tidy made some suggestions

[oharboe]

It would be interesting to run this on megaboom. megaboom has a 50% reduction in instances after hierarchical synthesis if the same(?) is done by naja edit.

@jeffng-or @maliberty FYI

[maliberty]

I think naja also does constant propagation which could be another item of interest in OR.

[maliberty]

I don't yet see the clang-tidy thumbs up

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[povik]

@maliberty tooling is happy now (expect for CI which seems to fail for an external reason)

[povik]

constant propagation which could be another item of interest in OR.

I see OpenSTA does some constant propagation for its own purposes, the result of which is available under sta_->simLogicValue(Pin*), but I don't think we can reuse it directly

Some of the constants originate from tie-low/tie-high cells, but there are also constants sourced from SDC:

void
Sim::seedConstants()
{
  // Propagate constants from inputs tied hi/low in the network.
  enqueueConstantPinInputs();
  // Propagate set_LogicValue::zero, set_LogicValue::one, set_logic_dc constants.
  setConstraintConstPins(sdc_->logicValues());
  // Propagate set_case_analysis constants.
  setConstraintConstPins(sdc_->caseLogicValues());
  // Propagate 0/1 constant functions.
  setConstFuncPins();
}

Especially set_case_analysis looks like something the design tool should not propagate into the logic and replace the logic with

[maliberty]

set_case_analysis is more for modelling a particular operating mode and we wouldn't want to remove logic based on it (it could be used in another mode). Netlist constants should be the basis for logic removal.

[povik]

That's what I thought

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[maliberty]

It would be good to have at least one unit test.

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"