- clone the repo
- open modelsim
- File -> new project
- Select the repo for project folder and name it whatever you want
- It will prompt you to add existing files. Add the
.vhd
files. - Now in the project window select the VHDL files and make sure the disable optization is check in compiler options
- Right click and hit compile.
- In the library view double click
work
->testbench
. This will start a simulation - Execute macro:
Tools
->tcl
->execute macro
- select
.do
file that you want to run.
- Don't be a jerk.
- Share your changes. We are share our changes with you.
- Make Testbench
- fill in architeture