T-HEAD c910 RVB-ICE Benchmark

[archanox]

| T-HEAD c910 ice | ~1200 MHz | 5.10 | Debian GNU/Linux bookworm/sid riscv64 | 1760 | 24420 | 26930 | 3340 | 6470 | - | http://ix.io/41AB |

[ThomasKaiser]

Thank you! Is this real silicon or FPGA? If the former how's that system called?

[archanox]

Hi @ThomasKaiser this is actual hardware. Specifically using one of T-head's BSP Debian images. If there's anything you'd like me to check or test, let me know.

https://occ.t-head.cn/vendor/detail/index?id=3906780664213024768&vendorId=3706716635429273600&module=4&key=download#sticky

AU $601.43 | T-head RVB-ICE Development Board,Dual-core XuanTie C910 RISC-V 64GC ,1.2GHz, Support Android/Debian System
https://a.aliexpress.com/_mrIQlPk

[ThomasKaiser]

@archanox I added today 'Geekbench piggyback mode' to sbc-bench to ensure proper monitoring of the benchmark.

If time allows could you grab latest version from here and test on RISC-V machines? Executing sbc-bench.sh -G is all that's needed (and a few 100 MB space below /usr/local/src/ since at least on ARM those Geekbench binaries are rather fat).

Results should then somehow look like this: http://ix.io/48Jx

[archanox]

So for the c910 I got http://ix.io/48Zu

But I also got the following output

debian@thead-910:~$ sudo ./sbc-bench.sh -G

Average load and/or CPU utilization too high (too much background activity). Waiting...

Too busy for benchmarking: 11:43:00 up 24 min,  5 users,  load average: 0.09, 0.22, 0.37,  cpu: 10%

sbc-bench v0.9.8 taking care of Geekbench

Installing needed tools: apt -f -qq -y install links, geekbench 5.4.5. Done.
Checking cpufreq OPP. Done.
Executing RAM latency tester. Done.
Executing Geekbench..../sbc-bench.sh: line 2361:  2583 Illegal instruction     "${GBBinary}" > ${TempLog} 2>&1
./sbc-bench.sh: line 2361:  2683 Illegal instruction     "${GBBinary}" > ${TempLog2} 2>&1
 Faile Done.
Checking cpufreq OPP. Done (5 minutes elapsed).

Scores not valid. Throttling occured and/or too much background activity.

Full results uploaded to http://ix.io/48Zu. Please check the log for anomalies (e.g. swapping
or throttling happenend).

[ThomasKaiser]

Thank you, so Geekbench doesn't even run on your board. When searching in the results list there are only single-core results (most probably Allwinner D1) and emulations so I guess it's normal that it doesn't run on the c910: https://browser.geekbench.com/search?q=riscv64

[archanox]

It's strange that there are so many single core results there, perhaps Geekbench has a bug with discerning harts and processors.
Contrary to what you've guess no T-head based chip will appear there due to some problematic instruction. This includes the c906 and c910, the former found in the D1.

[ThomasKaiser]

perhaps Geekbench has a bug with discerning harts and processors.

Ah yes, Geekbench fails just like on ARM getting CPU core/cluster details. But you need to click on individual results to be aware of that.

Wrt problematic instruction are you refering to FENCE.TSO or even more?

[archanox]

Yeah I think that’s it. @brucehoult was the one that made me aware of it originally outside of that post.

[brucehoult]

I think a trap-and-emulate fix for FENCE.TSO has been upstreamed into OpenSBI.

[ThomasKaiser]

@Icenowy was so kind to execute both sbc-bench (results) and Geekbench (results) on JH7110. The 1750 MHz cpufreq are a nice surprise though missing crypto acceleration will negatively affect 'combined scores' of certain benchmarks.

To 'benchmark the benchmark' I used ARMv8 SoCs w/o ARMv8 Crypto Extensions as comparison:

• JH7110 vs. Amlogic S905 (quad A53 at 1.5 GHz)
• JH7110 vs. Broadcom BCM2711 (quad A72 at 1.8 GHz)

[brucehoult]

missing crypto acceleration will negatively affect 'combined scores' of certain benchmarks

Note that the JH7110 doesn't have the RISC-V "scalar crypto" extension (it uses U74 21G1 cores, which of course are well before the extension was rafitied), but it DOES HAVE hardware acceleration for SHA and AES and something else I can't recall now. Just need to plumb some appropriate library routines through to the (I assume) memory-mapped accelerators.