Source code fixes to get everything to compile with the Xilinx toolch…

…ain and also use block RAMs instead of flipflops for the register files.

src/verilog/rtl/decode/decode.v

@@ -167,7 +167,7 @@ wire ext_literal_s3; //VIN
 wire long_instr_or_literal_required;
 wire [31:0] imm1_frominstr_fromliteral;
 reg [31:0] issue_imm_value1;
-reg [9:0] s3_field_const; //VIN
+wire [9:0] s3_field_const; //VIN
 
 
 wire [32:0] s1_fp_constant;

src/verilog/rtl/fpga/reg_128x32b_3r_2w_fpga.v

@@ -0,0 +1,91 @@
+module reg_128x32b_3r_2w_fpga
+(/*AUTOARG*/
+   // Outputs
+   rd0_data, rd1_data, rd2_data,
+   // Inputs
+   clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr1_addr, wr0_en,
+   wr1_en, wr0_data, wr1_data
+   );
+input clk;
+
+output [31:0] rd0_data;
+output [31:0] rd1_data;
+output [31:0] rd2_data;
+
+input [6:0] rd0_addr;
+input [6:0] rd1_addr;
+input [6:0] rd2_addr;
+
+input [6:0] wr0_addr;
+input [6:0] wr1_addr;
+
+input wr0_en;
+input wr1_en;
+
+input [31:0] wr0_data;
+input [31:0] wr1_data;
+
+wire [6:0] wr_addr;
+wire [9:0] wr_addr_blk;
+wire wr_en;
+wire [31:0] wr_data;
+
+wire [9:0] rd0_addr_blk;
+wire [9:0] rd1_addr_blk;
+wire [9:0] rd2_addr_blk;
+
+assign rd0_addr_blk = {3'b000, rd0_addr};
+assign rd1_addr_blk = {3'b000, rd1_addr};
+assign rd2_addr_blk = {3'b000, rd2_addr};
+
+assign wr_data = wr1_en ? wr1_data : wr0_data;
+assign wr_addr = wr1_en ? wr1_addr : wr0_addr;
+assign wr_addr_blk = {3'b000, wr_addr};
+assign wr_en = wr0_en | wr1_en;
+
+block_ram bank0(
+  .clka(clk), // input clka
+  //.rsta(rst), // input rsta
+  .wea(wr_en), // input [3 : 0] wea
+  .addra(wr_addr_blk), // input [31 : 0] addra
+  .dina(wr_data), // input [31 : 0] dina
+  .douta(), // output [31 : 0] douta
+  .clkb(clk), // input clkb
+  //.rstb(rst), // input rstb
+  .web(1'b0), // input [3 : 0] web
+  .addrb(rd0_addr_blk), // input [31 : 0] addrb
+  .dinb(32'd0), // input [31 : 0] dinb
+  .doutb(rd0_data) // output [31 : 0] doutb
+);
+
+block_ram bank1(
+  .clka(clk), // input clka
+  //.rsta(rst), // input rsta
+  .wea(wr_en), // input [3 : 0] wea
+  .addra(wr_addr_blk), // input [31 : 0] addra
+  .dina(wr_data), // input [31 : 0] dina
+  .douta(), // output [31 : 0] douta
+  .clkb(clk), // input clkb
+  //.rstb(rst), // input rstb
+  .web(1'b0), // input [3 : 0] web
+  .addrb(rd1_addr_blk), // input [31 : 0] addrb
+  .dinb(32'd0), // input [31 : 0] dinb
+  .doutb(rd1_data) // output [31 : 0] doutb
+);
+
+block_ram bank2(
+  .clka(clk), // input clka
+  //.rsta(rst), // input rsta
+  .wea(wr_en), // input [3 : 0] wea
+  .addra(wr_addr_blk), // input [31 : 0] addra
+  .dina(wr_data), // input [31 : 0] dina
+  .douta(), // output [31 : 0] douta
+  .clkb(clk), // input clkb
+  //.rstb(rst), // input rstb
+  .web(1'b0), // input [3 : 0] web
+  .addrb(rd2_addr_blk), // input [31 : 0] addrb
+  .dinb(32'd0), // input [31 : 0] dinb
+  .doutb(rd2_data) // output [31 : 0] doutb
+);
+
+endmodule

src/verilog/rtl/fpga/reg_256x32b_3r_1w_fpga.v

@@ -0,0 +1,79 @@
+module reg_256x32b_3r_1w_fpga
+  (/*AUTOARG*/
+   // Outputs
+   rd0_data, rd1_data, rd2_data,
+   // Inputs
+   clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_data
+   );
+   input clk;
+
+   output [31:0] rd0_data;
+   output [31:0] rd1_data;
+   output [31:0] rd2_data;
+
+   input [9:0]   rd0_addr;
+   input [9:0]   rd1_addr;
+   input [9:0]   rd2_addr;
+
+   input [9:0]   wr0_addr;
+
+   input   wr0_en;
+
+   input [31:0]  wr0_data;
+
+wire [31:0] block_out_a;
+wire [31:0] block_out_b;
+wire [31:0] block_out_c;
+
+reg wr_en_a;
+
+assign rd0_data = block_out_a;
+assign rd1_data = block_out_b;
+assign rd2_data = block_out_c;
+
+block_ram bank0(
+  .clka(clk), // input clka
+  //.rsta(rst), // input rsta
+  .wea(wr0_en), // input [3 : 0] wea
+  .addra(wr0_addr), // input [31 : 0] addra
+  .dina(wr0_data), // input [31 : 0] dina
+  .douta(), // output [31 : 0] douta
+  .clkb(clk), // input clkb
+  //.rstb(rst), // input rstb
+  .web(4'd0), // input [3 : 0] web
+  .addrb(rd0_addr), // input [31 : 0] addrb
+  .dinb(32'd0), // input [31 : 0] dinb
+  .doutb(block_out_a) // output [31 : 0] doutb
+);
+
+block_ram bank1(
+  .clka(clk), // input clka
+  //.rsta(rst), // input rsta
+  .wea(wr0_en), // input [3 : 0] wea
+  .addra(wr0_addr), // input [31 : 0] addra
+  .dina(wr0_data), // input [31 : 0] dina
+  .douta(), // output [31 : 0] douta
+  .clkb(clk), // input clkb
+  //.rstb(rst), // input rstb
+  .web(4'd0), // input [3 : 0] web
+  .addrb(rd1_addr), // input [31 : 0] addrb
+  .dinb(32'd0), // input [31 : 0] dinb
+  .doutb(block_out_b) // output [31 : 0] doutb
+);
+
+block_ram bank2(
+  .clka(clk), // input clka
+  //.rsta(rst), // input rsta
+  .wea(wr0_en), // input [3 : 0] wea
+  .addra(wr0_addr), // input [31 : 0] addra
+  .dina(wr0_data), // input [31 : 0] dina
+  .douta(), // output [31 : 0] douta
+  .clkb(clk), // input clkb
+  //.rstb(rst), // input rstb
+  .web(4'd0), // input [3 : 0] web
+  .addrb(rd2_addr), // input [31 : 0] addrb
+  .dinb(32'd0), // input [31 : 0] dinb
+  .doutb(block_out_c) // output [31 : 0] doutb
+);
+
+endmodule

src/verilog/rtl/rfa/rfa.v

@@ -49,8 +49,8 @@ module rfa(/*AUTOARG*/
    wire [31:0] 	 dummy_next_highest_priority;
 
    //**change [psp]
-   reg lsu_wait;
-   reg lsu_wr_req_lp;
+   wire lsu_wait;
+   wire lsu_wr_req_lp;
 
    // If lsu requests writes, it bypasses the priority encoder
    // but if salu request writes, it bypasses both

src/verilog/rtl/salu/salu.vp

@@ -62,7 +62,6 @@ module salu(
 		exec_rd_exec_value, exec_rd_vcc_value;
 
    //**CHANGE [PSP]
-   reg rfa2salu_req_hold;
    output rfa2sgpr_request;
 
    output 	exec_wr_exec_en, exec_wr_vcc_en, exec_wr_m0_en, exec_wr_scc_en,
@@ -116,6 +115,7 @@ module salu(
    reg [31:0] 	 exec_rd_m0_value_i;
    reg [63:0] exec_rd_exec_value_i, exec_rd_vcc_value_i;
    wire [63:0] sgpr_source2_data_i, sgpr_source1_data_i;
+   wire rfa2salu_req_hold;
 
    // Keep the delay on exec signals
    always @ ( posedge clk or posedge rst ) begin

src/verilog/rtl/salu/salu_controller.v

@@ -68,7 +68,7 @@ reg [31:0] alu_control;
 reg salu2sgpr_req;
 reg salu2sgpr_req_trig;
 
-reg sgpr_fw_check;
+wire sgpr_fw_check;
 assign sgpr_fw_check = {control_en_fw, dst_reg_fw[11:9]} && 4'b1110;
 //**
 

src/verilog/rtl/sgpr/reg_512x32b_3r_2w.v

@@ -105,7 +105,12 @@ module reg_512x32b_3r_2w
    reg [31:0] 	  wr1_data_bank3;
    //see mux at end of module
 
-   reg_128x32b_3r_2w bank0(
+`ifdef FPGA_BUILD
+  reg_128x32b_3r_2w_fpga
+`else
+  reg_128x32b_3r_2w
+`endif
+  bank0(
 			   .rd0_addr(rd0_addr_bank0),
 			   .rd0_data(rd0_data_bank0),
 			   .rd1_addr(rd1_addr_bank0),
@@ -121,7 +126,12 @@ module reg_512x32b_3r_2w
 			   .clk(clk)
 			   );
 
-   reg_128x32b_3r_2w bank1(
+`ifdef FPGA_BUILD
+  reg_128x32b_3r_2w_fpga
+`else
+  reg_128x32b_3r_2w
+`endif
+  bank1(
 			   .rd0_addr(rd0_addr_bank1),
 			   .rd0_data(rd0_data_bank1),
 			   .rd1_addr(rd1_addr_bank1),
@@ -137,7 +147,12 @@ module reg_512x32b_3r_2w
 			   .clk(clk)
 			   );
 
-   reg_128x32b_3r_2w bank2(
+`ifdef FPGA_BUILD
+  reg_128x32b_3r_2w_fpga
+`else
+  reg_128x32b_3r_2w
+`endif
+  bank2(
 			   .rd0_addr(rd0_addr_bank2),
 			   .rd0_data(rd0_data_bank2),
 			   .rd1_addr(rd1_addr_bank2),
@@ -153,7 +168,12 @@ module reg_512x32b_3r_2w
 			   .clk(clk)
 			   );
 
-   reg_128x32b_3r_2w bank3(
+`ifdef FPGA_BUILD
+  reg_128x32b_3r_2w_fpga
+`else
+  reg_128x32b_3r_2w
+`endif
+  bank3(
 			   .rd0_addr(rd0_addr_bank3),
 			   .rd0_data(rd0_data_bank3),
 			   .rd1_addr(rd1_addr_bank3),

src/verilog/rtl/vgpr/reg_1024x32b_3r_1w.v

@@ -65,18 +65,22 @@ module reg_1024x32b_3r_1w (/*AUTOARG*/
 	rd2_data <= rd2_data_bank0;
 
      end
-
-   reg_256x32b_3r_1w bank0(
-			   .rd0_addr(rd0_addr),
-			   .rd0_data(rd0_data_bank0),
-			   .rd1_addr(rd1_addr),
-			   .rd1_data(rd1_data_bank0),
-			   .rd2_addr(rd2_addr),
-			   .rd2_data(rd2_data_bank0),
-			   .wr0_addr(wr0_addr), //connect write address straight in
-			   .wr0_en(wr0_en[0]|wr0_en[1]|wr0_en[2]|wr0_en[3]),  //only focus on 32b, so only enable if bottom bit active high
-			   .wr0_data(wr0_data[31:0]),
-			   .clk(clk)
-			   );
+`ifdef FPGA_BUILD
+  reg_256x32b_3r_1w_fpga
+`else
+  reg_256x32b_3r_1w
+`endif
+   bank0(
+    .rd0_addr(rd0_addr),
+    .rd0_data(rd0_data_bank0),
+    .rd1_addr(rd1_addr),
+    .rd1_data(rd1_data_bank0),
+    .rd2_addr(rd2_addr),
+    .rd2_data(rd2_data_bank0),
+    .wr0_addr(wr0_addr), //connect write address straight in
+    .wr0_en(wr0_en[0]|wr0_en[1]|wr0_en[2]|wr0_en[3]),  //only focus on 32b, so only enable if bottom bit active high
+    .wr0_data(wr0_data[31:0]),
+    .clk(clk)
+  );
 
 endmodule